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mannraval1/README.md

Hi, I'm Mann Raval! ๐Ÿ‘‹ ๐Ÿ‘จโ€๐Ÿ’ป

๐Ÿš€ Passionate VLSI & Embedded Systems Engineer

I specialize in Digital Design and Verification, bridging the gap between hardware architecture and efficient software implementation. โšก


๐Ÿ›  Technical Toolbox

  • Hardware Design: Verilog ๐Ÿ—๏ธ, SystemVerilog ๐Ÿงช, FPGA Design (Intel/Quartus) ์นฉ, RTL Design ๐Ÿ’พ
  • Programming: C ๐Ÿ’ป, C++ ๐Ÿ–ฅ๏ธ, Python ๐Ÿ, MATLAB ๐Ÿ“Š
  • Specialties: Digital Verification โœ…, Physical Design ๐Ÿ› ๏ธ, I2C Protocols ๐Ÿ“ก
  • Tools: Genus ๐Ÿ› ๏ธ, Innovus โšก, Vivado ๐Ÿ”Œ, ModelSim ๐Ÿ”

๐Ÿ“‚ Featured Projects

  • HDLBits Solutions ๐Ÿ“: Comprehensive solutions for logic design problems to master Verilog.
  • SCD4x I2C Driver ๐ŸŒก๏ธ: Low-level C implementation for high-precision sensor data communication.
  • RF Antenna Design ๐Ÿ“ก: 1GHz Cylindrical Reflector simulations for signal optimization.
  • Music Extraction ๐ŸŽน: Utilizing Signal Processing to bridge my love for piano and technology.

๐ŸŽ๏ธ Beyond the Code

  • MS Dhoni Fan: Inspired by the leadership, legendary finishing, and composure of "Captain Cool." ๐Ÿ ๐ŸงŠ
  • F1 Enthusiast: Big fan of Max Verstappen and the high-speed engineering behind the cars! ๐Ÿ
  • Musician: I enjoy spending my free time learning and playing notes on the piano. ๐ŸŽน ๐ŸŽต
  • Gamer: Usually found exploring new titles on my Steam Deck or OMEN gaming laptop. ๐ŸŽฎ ๐Ÿ’ป

๐Ÿ“ซ Let's Connect!

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  1. Machine-to-Machine-Communication Machine-to-Machine-Communication Public

    C++ implementation of a robust M2M communication framework using socket programming for real-time data exchange.

    C++ 1

  2. HDLBits-Solutions HDLBits-Solutions Public

    This repo has the solutions for the HDLBits Problem Set

    Verilog

  3. RTL RTL Public

    This repository is a structured technical library dedicated to Register Transfer Level (RTL) engineering. It serves as a centralized hub for digital design patterns, showcasing the implementation oโ€ฆ

    Verilog

  4. Sync-FIFO Sync-FIFO Public

    A parameterized Synchronous FIFO implementation in Verilog, featuring a single-clock architecture, robust full/empty flag detection, and a Verilator-based C++ verification environment with GTKWave โ€ฆ

    Verilog