Synchronous FIFO (First In, First Out)

Overview

A Synchronous FIFO is a memory buffer used to store and retrieve data sequentially, where both write and read operations occur under the same clock domain. This design is commonly used in digital systems to buffer data between two subsystems that operate with the same clock but at different data processing speeds.

Key Characteristics

• Single Clock: One clock signal controls both read and write operations.
• Sequential Access: Data is written into the FIFO sequentially.
• Order Preservation: The first data written is the first data read (FIFO property), ensuring predictable and reliable data flow.

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FIFO Concept & Architecture

The FIFO ensures data integrity in pipelined and buffered systems by maintaining the exact order of data.

Operations

1. Write Operation: Data is written at the write_pointer location. The pointer increments after a successful write. This is only permitted when full is low.
2. Read Operation: Data is retrieved from the read_pointer location. The pointer increments after a successful read. This is only permitted when empty is low.
3. Status Flags: * Full: Triggered when the write pointer catches up to the read pointer.
   • Empty: Triggered when the read pointer catches up to the write pointer.

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FIFO Interface Signals

Signal Name	Description
clk	Clock signal (common for read and write)
reset	System reset (active high/low depending on RTL)
cs	Chip Select
wr_en	Write Enable
rd_en	Read Enable
data_input	Input data bus
data_output	Output data bus
full	FIFO full indicator (prevents overflows)
empty	FIFO empty indicator (prevents underflows)

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Design Details

• Clock Domains: Single clock domain.
• Read Type: Registered read output.
• Parameterization: Supports configurable Data Width and FIFO Depth.
• Detection: Count-based Full/Empty detection.
• Wrap Handling: Pointer wraparound supported (suitable for power-of-two and non-power-of-two depths).

Project Directory Structure

. ├── rtl/ │ └── sync_fifo.v # Core FIFO Logic ├── tb/ │ └── sync_fifo_tb.v # Testbench ├── build/ │ └── (generated files) # Simulation artifacts ├── Makefile # Build automation └── README.md # Documentation

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Tools Required

• Verilator: RTL simulation
• GTKWave: Waveform viewing
• C++ Compiler: C++20 support required for Verilator timing

How to Run

1. Clean previous build artifacts:

   make clean

2. To display waveforms:

    make wave