This repository contains my personal solutions to the HDLBits problem sets. HDLBits is a collection of small circuit design problems for practicing digital logic using Verilog.
Total Problems Solved: ~113 / 181
| Category | Status |
|---|---|
| 01. Basics | ✅ Completed |
| 02. Vectors | ✅ Completed |
| 03. Modules | ✅ Completed |
| 04. Procedures | ✅ Completed |
| 05. More Verilog Features | ✅ Completed |
| 06. Combinational Logic | ✅ Completed |
| 07. Sequential Logic | ✅ Completed |
| 08. More Circuits | 🛠️ In Progress |
The solutions are organized by the original HDLBits curriculum sections:
01-Basics/: Simple gates, wires, and introductory problems.02-Vectors/: Working with bus widths, bitwise operations, and replication.03-Module/: Instantiating modules and connecting ports.04-Procedures/: Always blocks, if/case statements, and blocking/non-blocking assignments.05-More Verilog Features/: Loops, generate blocks, and vector reduction.06-Combinational Logic/: Arithmetic circuits and multiplexers.07-Sequential Logic/: Flip-flops, counters, and Finite State Machines (FSM).
- Clone the repository:
git clone [https://github.com/mannraval1/HDLBits-Solutions.git](https://github.com/mannraval1/HDLBits-Solutions.git)