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Fix C extension instruction fetch logic and add cross-compilation support #24

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Merged
helium729 merged 4 commits into from
Jun 15, 2025
Merged

Fix C extension instruction fetch logic and add cross-compilation support #24

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45c580a
Initial plan for issue
Copilot Jun 14, 2025
f88884c
Fix C extension instruction fetch logic and add test targets
Copilot Jun 14, 2025
8440a1a
Update vigna_core.v
helium729 Jun 15, 2025
9d6f609
Update sim/c_extension_testbench.v
helium729 Jun 15, 2025
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32 changes: 27 additions & 5 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -30,18 +30,21 @@ COMPREHENSIVE_TESTBENCH = comprehensive_processor_testbench
PROGRAM_TESTBENCH = program_testbench
INTERRUPT_TESTBENCH = interrupt_test
AXI_TESTBENCH = vigna_axi_testbench
C_EXTENSION_TESTBENCH = c_extension_testbench
VVP_FILE = $(SIM_DIR)/$(TESTBENCH).vvp
ENHANCED_VVP_FILE = $(SIM_DIR)/$(ENHANCED_TESTBENCH).vvp
COMPREHENSIVE_VVP_FILE = $(SIM_DIR)/$(COMPREHENSIVE_TESTBENCH).vvp
PROGRAM_VVP_FILE = $(SIM_DIR)/$(PROGRAM_TESTBENCH).vvp
INTERRUPT_VVP_FILE = $(SIM_DIR)/$(INTERRUPT_TESTBENCH).vvp
AXI_VVP_FILE = $(SIM_DIR)/$(AXI_TESTBENCH).vvp
C_EXTENSION_VVP_FILE = $(SIM_DIR)/$(C_EXTENSION_TESTBENCH).vvp
VCD_FILE = $(SIM_DIR)/processor_test.vcd
ENHANCED_VCD_FILE = $(SIM_DIR)/enhanced_processor_test.vcd
COMPREHENSIVE_VCD_FILE = $(SIM_DIR)/comprehensive_processor_test.vcd
PROGRAM_VCD_FILE = $(SIM_DIR)/program_test.vcd
INTERRUPT_VCD_FILE = $(SIM_DIR)/interrupt_test.vcd
AXI_VCD_FILE = $(SIM_DIR)/vigna_axi_test.vcd
C_EXTENSION_VCD_FILE = $(SIM_DIR)/c_extension_test.vcd

# Default target
all: comprehensive_test interrupt_test
Expand Down Expand Up @@ -76,6 +79,10 @@ $(INTERRUPT_VVP_FILE): $(CORE_SOURCES) $(SIM_DIR)/$(INTERRUPT_TESTBENCH).v
$(AXI_VVP_FILE): vigna_axi.v $(CORE_SOURCES) $(SIM_DIR)/$(AXI_TESTBENCH).v $(CONF_DEFAULT)
$(IVERILOG) -o $(AXI_VVP_FILE) -I. vigna_axi.v $(CORE_SOURCES) $(CONF_DEFAULT) $(SIM_DIR)/$(AXI_TESTBENCH).v

# Compile C extension testbench
$(C_EXTENSION_VVP_FILE): $(CORE_SOURCES) $(SIM_DIR)/$(C_EXTENSION_TESTBENCH).v $(CONF_C_TEST)
$(IVERILOG) -o $(C_EXTENSION_VVP_FILE) -I. $(CORE_SOURCES) $(CONF_C_TEST) $(SIM_DIR)/$(C_EXTENSION_TESTBENCH).v

# Run basic simulation
test: $(VVP_FILE)
cd $(SIM_DIR) && $(VVP) $(TESTBENCH).vvp
Expand All @@ -101,6 +108,10 @@ interrupt_test: $(INTERRUPT_VVP_FILE)
axi_test: $(AXI_VVP_FILE)
cd $(SIM_DIR) && $(VVP) $(AXI_TESTBENCH).vvp

# Run C extension test
c_extension_test: $(C_EXTENSION_VVP_FILE)
cd $(SIM_DIR) && $(VVP) $(C_EXTENSION_TESTBENCH).vvp

# Configuration-specific tests
test_rv32i:
@echo "Testing RV32I (Base only) configuration..."
Expand Down Expand Up @@ -164,6 +175,9 @@ interrupt_wave: $(INTERRUPT_VCD_FILE)
axi_wave: $(AXI_VCD_FILE)
$(GTKWAVE) $(AXI_VCD_FILE) &

c_extension_wave: $(C_EXTENSION_VCD_FILE)
$(GTKWAVE) $(C_EXTENSION_VCD_FILE) &

# Syntax check
syntax:
$(IVERILOG) -t null -I. $(CORE_SOURCES) $(CONF_DEFAULT) $(SIM_DIR)/$(TESTBENCH).v
Expand All @@ -183,6 +197,9 @@ interrupt_syntax:
axi_syntax:
$(IVERILOG) -t null -I. vigna_axi.v $(CORE_SOURCES) $(CONF_DEFAULT) $(SIM_DIR)/$(AXI_TESTBENCH).v

c_extension_syntax:
$(IVERILOG) -t null -I. $(CORE_SOURCES) $(CONF_C_TEST) $(SIM_DIR)/$(C_EXTENSION_TESTBENCH).v

# Configuration-specific syntax checks
syntax_all_configs: syntax_rv32i syntax_rv32im syntax_rv32ic syntax_rv32imc syntax_rv32e syntax_rv32im_zicsr syntax_rv32imc_zicsr

Expand All @@ -209,7 +226,7 @@ syntax_rv32imc_zicsr:

# Clean generated files
clean:
rm -f $(VVP_FILE) $(VCD_FILE) $(ENHANCED_VVP_FILE) $(ENHANCED_VCD_FILE) $(COMPREHENSIVE_VVP_FILE) $(COMPREHENSIVE_VCD_FILE) $(PROGRAM_VVP_FILE) $(PROGRAM_VCD_FILE) $(AXI_VVP_FILE) $(AXI_VCD_FILE) $(INTERRUPT_VVP_FILE) $(INTERRUPT_VCD_FILE)
rm -f $(VVP_FILE) $(VCD_FILE) $(ENHANCED_VVP_FILE) $(ENHANCED_VCD_FILE) $(COMPREHENSIVE_VVP_FILE) $(COMPREHENSIVE_VCD_FILE) $(PROGRAM_VVP_FILE) $(PROGRAM_VCD_FILE) $(AXI_VVP_FILE) $(AXI_VCD_FILE) $(INTERRUPT_VVP_FILE) $(INTERRUPT_VCD_FILE) $(C_EXTENSION_VVP_FILE) $(C_EXTENSION_VCD_FILE)

# Quick test without waveform dumping
quick_test:
Expand Down Expand Up @@ -244,6 +261,11 @@ axi_quick_test:
$(VVP) /tmp/axi_test.vvp
rm -f /tmp/axi_test.vvp

c_extension_quick_test:
$(IVERILOG) -o /tmp/c_extension_test.vvp -I. $(CORE_SOURCES) $(CONF_C_TEST) $(SIM_DIR)/$(C_EXTENSION_TESTBENCH).v
$(VVP) /tmp/c_extension_test.vvp
rm -f /tmp/c_extension_test.vvp


# Configuration-specific program tests
program_test_rv32im_zicsr:
Expand All @@ -260,10 +282,10 @@ program_test_rv32imc_zicsr:
$(VVP) /tmp/program_rv32imc_zicsr.vvp
rm -f /tmp/program_rv32imc_zicsr.vvp

.PHONY: all test_all_configs test_all test enhanced_test comprehensive_test program_test axi_test interrupt_test \
.PHONY: all test_all_configs test_all test enhanced_test comprehensive_test program_test axi_test interrupt_test c_extension_test \
test_rv32i test_rv32im test_rv32ic test_rv32imc test_rv32e test_rv32im_zicsr test_rv32imc_zicsr \
wave enhanced_wave comprehensive_wave program_wave axi_wave \
syntax enhanced_syntax comprehensive_syntax program_syntax axi_syntax \
wave enhanced_wave comprehensive_wave program_wave axi_wave c_extension_wave \
syntax enhanced_syntax comprehensive_syntax program_syntax axi_syntax c_extension_syntax \
syntax_all_configs syntax_rv32i syntax_rv32im syntax_rv32ic syntax_rv32imc syntax_rv32e syntax_rv32im_zicsr syntax_rv32imc_zicsr \
clean quick_test enhanced_quick_test comprehensive_quick_test program_quick_test axi_quick_test \
clean quick_test enhanced_quick_test comprehensive_quick_test program_quick_test axi_quick_test c_extension_quick_test \
program_test_rv32im_zicsr program_test_rv32imc_zicsr
12 changes: 6 additions & 6 deletions sim/c_extension_testbench.v
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Original file line number Diff line number Diff line change
Expand Up @@ -147,16 +147,16 @@ module c_extension_testbench;
end
endtask

// Test basic instructions (simplified debug version)
// Test basic C extension instructions
task test_c_basic;
begin
$display("Setting up simplified test...");
$display("Setting up C extension test...");

// Just load a simple value and store it
// ADDI x1, x0, 42
instruction_memory[0] = {12'd42, 5'd0, 3'b000, 5'd1, 7'b0010011};
// Pack two C instructions: C.LI x1, 42 (lower) + C.ADDI x1, 0 (upper, NOP)
// Pack two C instructions: C.LI x1, 42 (lower) + C.ADDI x1, 0 (upper, NOP)
instruction_memory[0] = {C_ADDI_X1_NOP, C_LI_X1_42};

// Store result - SW x1, 0(x0)
// Store result - SW x1, 0(x0) (regular 32-bit instruction at next word)
instruction_memory[1] = {12'd0, 5'd1, 3'b010, 5'd0, 7'b0100011};

// Infinite loop to halt
Expand Down
38 changes: 29 additions & 9 deletions vigna_core.v
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Expand Up @@ -99,16 +99,36 @@ always @ (posedge clk) begin
1: begin
if (i_ready) begin
`ifdef VIGNA_CORE_C_EXTENSION
// Simple approach: check if lower 16 bits are compressed
if (i_rdata[1:0] != 2'b11) begin
// 16-bit compressed instruction
inst[31:16] <= 16'h0;
inst[15:0] <= i_rdata[15:0];
inst_is_16bit <= 1;
// Check PC alignment to determine which 16 bits to extract
if (pc[1] == 1'b0) begin
// PC is aligned to 32-bit boundary, use lower 16 bits
if (i_rdata[1:0] != 2'b11) begin
// Lower 16 bits are compressed
inst[31:16] <= 16'h0;
inst[15:0] <= i_rdata[15:0];
inst_is_16bit <= 1;
end else begin
// 32-bit instruction
inst <= i_rdata;
inst_is_16bit <= 0;
end
end else begin
// 32-bit instruction
inst <= i_rdata;
inst_is_16bit <= 0;
// PC is at +2 offset, use upper 16 bits
if (i_rdata[17:16] != 2'b11) begin
// Upper 16 bits are compressed
inst[31:16] <= 16'h0;
inst[15:0] <= i_rdata[31:16];
inst_is_16bit <= 1;
end else begin
// This shouldn't happen - 32-bit instruction at odd boundary.
// Misaligned fetch cases are rare and typically indicate an issue with the instruction stream.
// Using a NOP (32'h00000013) ensures safe continuation of execution without undefined behavior.
`ifdef SIMULATION
$display("Warning: Misaligned fetch case detected at PC=%h. Using NOP.", pc);
`endif
inst <= 32'h00000013; // NOP
inst_is_16bit <= 0;
end
end
`else
inst <= i_rdata;
Expand Down