Fix C extension instruction fetch logic and add cross-compilation support#24
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Fix C extension instruction fetch logic and add cross-compilation support#24
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Co-authored-by: helium729 <30749877+helium729@users.noreply.github.com>
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[WIP] Bug fix
Fix C extension instruction fetch logic and add cross-compilation support
Jun 14, 2025
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Pull Request Overview
This PR fixes critical issues with the C extension instruction fetch logic and adds cross-compilation support. Key changes include:
- Updating instruction fetching in vigna_core.v to properly extract compressed instructions based on PC alignment.
- Enhancing the C extension testbench to cover both lower and upper 16-bit instruction extraction, including a fallback for misaligned fetches.
- Adding new Makefile targets for running, compiling, and cleaning up C extension tests and waveforms.
Reviewed Changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
| vigna_core.v | Improved fetch logic with PC alignment checks for compressed ops. |
| sim/c_extension_testbench.v | Updated testbench to use packed C extension instructions and refine display messages. |
| Makefile | Added targets and cleanup rules for C extension testing and cross-compilation. |
Comments suppressed due to low confidence (1)
Makefile:229
- Confirm that including the C_EXTENSION files in the cleanup process is intentional and consistent with the handling of other testbench artifacts.
rm -f $(VVP_FILE) $(VCD_FILE) ... $(C_EXTENSION_VVP_FILE) $(C_EXTENSION_VCD_FILE)
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
helium729
approved these changes
Jun 15, 2025
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This PR resolves critical issues with C extension tests and cross-compilation that were causing workflow failures.
Issues Fixed
1. C Extension Test Failures
The C extension tests were failing because the fetch logic didn't properly handle PC alignment when extracting 16-bit compressed instructions from 32-bit memory words.
Problem: When PC incremented by 2 after a compressed instruction, the processor would fetch from the same 32-bit word but incorrectly extract the lower 16 bits instead of the upper 16 bits.
Solution: Enhanced the fetch logic in
vigna_core.vto checkPC[1]alignment:PC[1] == 0: Extract lower 16 bits for compressed instructionsPC[1] == 1: Extract upper 16 bits for compressed instructions2. Cross-Compilation Issues
The workflow was skipping cross-compilation because the RISC-V toolchain wasn't available in the CI environment.
Solution: Added installation of
gcc-riscv64-linux-gnupackage to enable cross-compilation of C test programs.Test Results
All configuration tests now pass:
Additional Improvements
New Makefile Targets
Added comprehensive C extension test infrastructure:
c_extension_test: Run C extension testbenchc_extension_quick_test: Quick C extension test without waveformsc_extension_syntax: Syntax check for C extension testbenchc_extension_wave: View C extension test waveformsEnhanced Test Coverage
The C extension functionality is now properly tested in multiple configurations:
Before this fix, the comprehensive test suite showed:
After the fix:
Fixes #23.
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