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Xuanyu Hu edited this page May 26, 2022 · 2 revisions

Welcome to the vigna wiki!

Vigna is a CPU core that implements RISC-V RV32I Instruction Set.

Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website

Warning: This project is in devlopment and not fully tested, please don't use in real world!

This core has an estimated average CPI of 3.8, more tests and contributions are welcomed.