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Lab 2

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An-Ting Hsu edited this page Apr 23, 2015 · 2 revisions

FPGA Emulation

  • Due Date: 2015.03.20 Fri.

Objective

  • Introduce Xilinx demo board emulation flow.

Prerequisite

  • Fundamentals of logic gates.
  • Verilog HDL representation of Logic components.

Experiments

  1. Emulate exp1 in lab1 (a full adder s+cout=x+y+cin) with the following parameters.
    • x : T1
    • y : P2
    • cin : P1
    • s : H5
    • cout : H6
  2. Derive a BCD (i[3:0]) to 14-segment display decoder (D_ssd[14:0]), and also use four LEDs (d[3:0]) to monitor the 4-bit BCD number. (Other values of i outside the range will show F).

Lab Handouts : © Ma, Hsi-Pin, NTHUEE, Spring, 2015
Lab Codes : © Hsu, An Ting

[Home Page] (https://github.com/andyhsu10/LogicDesignLab/wiki)

Index

  1. [Introduction to Verilog HDL] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-1)
  2. [FPGA Emulation] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-2)
  3. [Counters] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-3)
  4. [Shift Registers] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-4)
  5. [Stop Watches] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-5)
  6. [Simple Calculator] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-6)
  7. [Electronic Clock I(Time Display)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-7)
  8. [Electronic Clock II(Multi-functions)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-8)
  9. [Speaker] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-9)
  10. [Electronic Organ] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-10)
  11. [LCD Display (1)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-11)
  12. [LCD Display (2)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-12)

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