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Lab 12
An-Ting Hsu edited this page Apr 23, 2015
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- Due Date: 2015.06.12 Fri.
- Implement the timer and stopwatch functions of the electronic clock.
- Fundamentals of logic gates.
- Logic modeling in Verilog HDL.
- Simple logic development and FSM control
- LCD control
- For the time delay of electronic clock in lab7. Instead using 14-segment displays to show the time, use LCD to present all the functions in lab7.
- (Bonus) Integrate the functions in lab7 and lab8 with LCD display.
[Home Page] (https://github.com/andyhsu10/LogicDesignLab/wiki)
- [Introduction to Verilog HDL] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-1)
- [FPGA Emulation] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-2)
- [Counters] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-3)
- [Shift Registers] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-4)
- [Stop Watches] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-5)
- [Simple Calculator] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-6)
- [Electronic Clock I(Time Display)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-7)
- [Electronic Clock II(Multi-functions)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-8)
- [Speaker] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-9)
- [Electronic Organ] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-10)
- [LCD Display (1)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-11)
- [LCD Display (2)] (https://github.com/andyhsu10/LogicDesignLab/wiki/Lab-12)