Lab 1

Introduction to Verilog HDL

• Due Date: 2015.03.13 Fri.

Objective

• Review fundamental logic components.
• Introduce Verilog HDL modeling and verification.

Prerequisite

• Fundamentals of logic gates.

Experiments

1. Design and implement a full adder. (s+cout=x+y+cin)
   1. Write the logic equation.
   2. Draw the related logic diagram.
   3. Verilog RTL representation with verification.
2. Design a single digit decimal adder with input A(a3``a2``a1``a0), B(b3``b2``b1``b0), Cin(ci), and output S(s3``s2``s1``s0) and Cout(co).
3. (Bonus) Design a 2-to-4-line decoder with enable (input in[1:0], enable en and output d[3:0]).
   1. Logic equation,
   2. Logic schematic,
   3. Verilog RTL representation with verification.