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This was done by cursor so its possible there are a couple things that aren't absolutely correct but looked good to me. |
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Fixed an error with an old helperfunc import and replaced with proper pyrtl function call.
Added script for calling output_to_verilog with pyrtl and using some other pyrtl functions to hopefully clean up the output.
Added some naming changes to pyrtl I/O ports made in tpu.py that pyrtl required for output_to_verilog.
gitignore file that is irrelevant.
Shouldn't have made anything that conflicts with design and already made stuff, but now the issues related to verilog output should be able to be closed!