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a question about the verilog version

Status: Open.

#9 In UCSBarchlab/OpenTPU;

· sherry-THRZ opened on Mar 15, 2025

bug report

Status: Open.

#8 In UCSBarchlab/OpenTPU;

· ferryuei opened on Feb 21, 2025

OutputToVerilog

Status: Open.

#7 In UCSBarchlab/OpenTPU;

· VincentJJY opened on Jan 18, 2024

ModuleNotFoundError: No module named 'gen_mem'

Status: Open.

#6 In UCSBarchlab/OpenTPU;

· John-12-27 opened on Sep 14, 2023

What block name should I use while generating the Verilog file using the output_to_verilog function?

Status: Open.

#5 In UCSBarchlab/OpenTPU;

· gmurali7 opened on Sep 1, 2022

does the Unified Buffer store data after im2col

Status: Open.

#4 In UCSBarchlab/OpenTPU;

· mosquito9910 opened on Jul 23, 2020

Edge deep learning

Status: Open.

#3 In UCSBarchlab/OpenTPU;

· rkgits opened on Apr 4, 2020

Question about compiling.

Status: Open.

#2 In UCSBarchlab/OpenTPU;

· nicolaswilde opened on Aug 24, 2019