SENT

Overview

This project is a SystemVerilog implementation of a SENT (Single Edge Nibble Transmission) protocol transmitter.

It generates a complete SENT frame including:

• Sync nibble (calibration pulse)
• Status nibble (fixed or dynamic)
• 6 data nibbles (fast channel)
• CRC nibble (4-bit checksum calculated over Status + Data nibbles)

Key Features

• Compliant with SAE J2716 SENT frame structure
• [SYNC] → [STATUS] → [DATA1] → [DATA2] → [DATA3] → [DATA4] → [DATA5] → [DATA6] → [CRC]

Output Waveform