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  • Villach, Austria
  • 17:31 (UTC +01:00)

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Pinned Loading

  1. AES AES Public

    Pipelined AES 128/192/256 Core Implementation

    VHDL

  2. high-speed-ieee754-floating-point-arithmetic-unit high-speed-ieee754-floating-point-arithmetic-unit Public

    RTL Implementation of a high speed IEEE-745 floating point arithematic unit

    VHDL 1

  3. RISC-V RISC-V Public

    Implementing a RISC-V Processor

    VHDL

  4. QSPI QSPI Public

    Quad Serial Peripheral Interface

    SystemVerilog

  5. ClassAB_Audio_Amplifier_with_Translinear_Loop ClassAB_Audio_Amplifier_with_Translinear_Loop Public

    Class_AB_Audio_Amplifier_with_Translinear_Loop

    1

  6. SENT SENT Public

    RTL Implementation of SENT - Single Edge Nibble Transmission for Automotive Applications

    SystemVerilog