Passionate about hardware design verification, formal methods, computer architecture, and building resilient, high-performance hardware systems.
Protocols:I2C, PCI Express, AXI, APB UART, AHB
Architectures: x86, RISC-V, MESI, MIPS-Lite
Focus: RTL Design, UVM, Formal Verification, DFT, Computer Architecture
- AXI3 Protocol Verification with SystemVerilog UVM
- Last-level cache with MESI coherence protocol implementation
- Formal property verification using Synopsys VC Formal
- Design-for-Test implementation and analysis
AXI3 Protocol Verification with SystemVerilog UVM
Designed a UVM verification environment and test plan for the AXI3 protocol, including address generation logic for wrap bursts and unaligned transfers with correct byte strobe handling. Developed scoreboards and checkers to validate master- slave communication using assertion-based verification.Last-Level Cache Simulation
Implemented 16MB, 16-way set associative cache simulation with MESI coherence protocol and pseudo-LRU replacement policy.MIPS-lite Pipeline Simulator
Developed 5-stage MIPS pipeline simulator in C that models both functional and timing behavior of a pipelined processor architecture.I2C Protocol Verification
Developed I2C master-slave verification setup with multi-master support, clock stretching, and repeated START functionality.- Hardware design/verification internship opportunities (June 2025)
- Open-source hardware verification collaborations
- RISC-V ecosystem and hardware verification communities
- Discussions on emerging computer architecture trends
Let's build something bug-free together! 🐞
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