designcompiler

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Example of a full DC synthesis script for a simple design

verilog synthesis synopsys vlsi designcompiler

Cardinal NIC and Chip Multiprocessor

verilog soc designcompiler innovus simvision

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

asic routing synthesis cts placement vlsi-physical-design pnr cmos digitaldesign icc2 floorplanning designcompiler timing-closure rtl-to-gdsii

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