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simulate axilite slave is ok when commit this lines; and rst is low a… #2

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simulate axilite slave is ok when commit this lines; and rst is low a… #2

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8 changes: 4 additions & 4 deletions sv/axi4lite_drv.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ class uvm_axi4lite_drv extends uvm_driver #(uvm_axi4lite_txn);
if (to_ctr == 31) begin
`uvm_error("uvm_axi4lite_master_driver","AWVALID timeout");
end
@(posedge vif.clk);
//@(posedge vif.clk);
vif.AWADDR <= 32'h0;
vif.AWPROT <= 3'h0;
vif.AWVALID <= 1'b0;
Expand All @@ -144,7 +144,7 @@ class uvm_axi4lite_drv extends uvm_driver #(uvm_axi4lite_txn);
if (to_ctr == 31) begin
`uvm_error("uvm_axi4lite_master_driver","ARVALID timeout");
end
@(posedge vif.clk);
//@(posedge vif.clk);
vif.ARADDR <= 32'h0;
vif.ARPROT <= 3'h0;
vif.ARVALID <= 1'b0;
Expand All @@ -158,15 +158,15 @@ class uvm_axi4lite_drv extends uvm_driver #(uvm_axi4lite_txn);
vif.WDATA <= data;
vif.WSTRB <= 4'hf;
vif.WVALID <= 1'b1;
@(posedge vif.clk);
//@(posedge vif.clk);
for(to_ctr = 0; to_ctr <= 31; to_ctr ++) begin
@(posedge vif.clk);
if (vif.WREADY) break;
end
if (to_ctr == 31) begin
`uvm_error("uvm_axi4lite_master_driver","AWVALID timeout");
end
@(posedge vif.clk);
//@(posedge vif.clk);
vif.WDATA <= 32'h0;
vif.WSTRB <= 4'h0;
vif.WVALID <= 1'b0;
Expand Down