Modules

Verilog descriptions are broken down into modules. A module is a container with inputs that can consume data, and outputs that can produce data, and contains the implementation of a circuit. A modules can contain instances of other modules, instances of gate level primitives, continuous assignments, and other more complex code structures that together describe the functionality of that module.

A module is declared using the module keyword along with a name for the module:

module mymod;

This declares a module named mymod with no ports. To add ports, we can list them in parentheses following the module name:

module mymod (port1, port2, port3);

Typically, we indicate the direction of those ports in the port list:

module mymod (input port1, input port2, output port3);

Subsequent ports with the same direction can be named in sequence without the port direction:

module mymod (input port1, port2, output port3);