LEDS interface I2S setup/async mode

components/i2s_out/esp32/dma.h

@@ -19,3 +19,15 @@ struct dma_desc {
   // linked list
   struct dma_desc *next;
 };
+
+/* Prepare desc for re-use after DMA EOF */
+static inline void i2s_dma_desc_reset(struct dma_desc *eof_desc)
+{
+  eof_desc->len = 0;
+  eof_desc->owner = 0;
+}
+
+static inline void i2s_dma_tx_get_des_addr(i2s_dev_t *hw, uint32_t *dscr_addr)
+{
+    *dscr_addr = hw->out_link_dscr;
+}

components/i2s_out/esp32/i2s.c

@@ -116,7 +116,7 @@ int i2s_out_i2s_setup(struct i2s_out *i2s_out, const struct i2s_out_options *opt
     i2s_out->dev->sample_rate_conf.val
   );
 
-  // reset eof state
+  // reset event state
   xEventGroupClearBits(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_I2S_EOF);
 
   return 0;
@@ -126,6 +126,9 @@ void i2s_out_i2s_start(struct i2s_out *i2s_out)
 {
   LOG_DEBUG("");
 
+  // reset event state
+  xEventGroupClearBits(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_I2S_EOF);
+
   taskENTER_CRITICAL(&i2s_out->mux);
 
   // NOTE: there seems to always be three extra BCK cycles at the start of TX
@@ -137,7 +140,7 @@ void i2s_out_i2s_start(struct i2s_out *i2s_out)
   taskEXIT_CRITICAL(&i2s_out->mux);
 }
 
-int i2s_out_i2s_flush(struct i2s_out *i2s_out)
+int i2s_out_i2s_flush(struct i2s_out *i2s_out, TickType_t timeout)
 {
   EventBits_t bits;
 
@@ -152,9 +155,16 @@ int i2s_out_i2s_flush(struct i2s_out *i2s_out)
 
     taskEXIT_CRITICAL(&i2s_out->mux);
 
-    LOG_DEBUG("wait event_group bits=%08x", I2S_OUT_EVENT_GROUP_BIT_I2S_EOF);
+    LOG_DEBUG("...");
+
+    bits = xEventGroupWaitBits(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_I2S_EOF, false, false, timeout);
 
-    xEventGroupWaitBits(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_I2S_EOF, false, false, portMAX_DELAY);
+    if (!(bits & I2S_OUT_EVENT_GROUP_BIT_I2S_EOF)) {
+      LOG_ERROR("timeout -> bits=%08x", bits);
+      return -1;
+    } else {
+      LOG_DEBUG("wait -> bits=%08x", bits);
+    }
   }
 
   return 0;
@@ -169,4 +179,7 @@ void i2s_out_i2s_stop(struct i2s_out *i2s_out)
   i2s_ll_tx_stop(i2s_out->dev);
 
   taskEXIT_CRITICAL(&i2s_out->mux);
+
+  // reset event state
+  xEventGroupClearBits(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_I2S_EOF);
 }

components/i2s_out/esp32/intr.c

@@ -17,9 +17,27 @@ static const int i2s_irq[I2S_PORT_MAX] = {
   [I2S_PORT_1]  = ETS_I2S1_INTR_SOURCE,
 };
 
+void IRAM_ATTR i2s_intr_out_total_eof_handler(struct i2s_out *i2s_out, BaseType_t *task_wokenp)
+{
+  uint32_t eof_addr;
+
+  i2s_ll_tx_get_eof_des_addr(i2s_out->dev, &eof_addr);
+
+  LOG_ISR_DEBUG("desc=%p", eof_addr);
+
+  // unblock flush() tasks
+  xEventGroupSetBitsFromISR(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_DMA_TOTAL_EOF, task_wokenp);
+
+  i2s_intr_clear(i2s_out->dev, I2S_OUT_TOTAL_EOF_INT_CLR);
+}
+
 void IRAM_ATTR i2s_intr_out_dscr_err_handler(struct i2s_out *i2s_out, BaseType_t *task_wokenp)
 {
-  LOG_ISR_WARN("");
+  uint32_t dscr_addr;
+
+  i2s_dma_tx_get_des_addr(i2s_out->dev, &dscr_addr);
+
+  LOG_ISR_WARN("desc=%p", dscr_addr);
 
   i2s_intr_clear(i2s_out->dev, I2S_OUT_DSCR_ERR_INT_CLR);
 }
@@ -32,14 +50,66 @@ void IRAM_ATTR i2s_intr_out_eof_handler(struct i2s_out *i2s_out, BaseType_t *tas
 
   struct dma_desc *eof_desc = (struct dma_desc *) eof_addr;
 
-  LOG_ISR_DEBUG("desc=%p", eof_desc);
+  // only handle normal out_desc, not repeat_desc or end_desc
+  if (eof_desc >= i2s_out->dma_out_desc && eof_desc < i2s_out->dma_out_desc + i2s_out->dma_out_count) {
+    LOG_ISR_DEBUG("eof desc=%p owner=%u len=%u", eof_desc, eof_desc->owner, eof_desc->len);
 
-  // NOTE: this is unlikely to stop DMA before this repeats at least once
-  i2s_ll_tx_stop_link(i2s_out->dev);
-  i2s_ll_rx_stop_link(i2s_out->dev);
+    // speculation: we may miss sone EOF ISRs
+    if (i2s_out->dma_eof_desc) {
+      for (struct dma_desc *desc = eof_desc; desc > i2s_out->dma_eof_desc; desc--) {
+        if (desc != eof_desc) {
+          LOG_ISR_WARN("miss desc=%p owner=%u len=%u", desc, desc->owner, desc->len);
+        }
 
-  // unblock flush() task
-  xEventGroupSetBitsFromISR(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_DMA_EOF, task_wokenp);
+        i2s_dma_desc_reset(desc);
+      }
+    } else {
+      i2s_dma_desc_reset(eof_desc);
+    }
+
+    i2s_out->dma_eof_desc = eof_desc;
+
+    // unblock get() task
+    xEventGroupSetBitsFromISR(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_DMA_EOF, task_wokenp);
+
+  } else if (eof_desc == i2s_out->dma_end_desc) {
+
+    // speculation: we might miss EOF ISR for an intermediate DMA descriptor, and hit TOTAL_EOF with eof_addr at the end_desc
+    // resulting in wait() deadlocking on dma_eof_desc not being updated
+    eof_desc = i2s_out->dma_out_desc + i2s_out->dma_out_count - 1;
+
+    if (!i2s_out->dma_eof_desc) {
+      LOG_ISR_WARN("end desc=%p owner=%u len=%u, dma_write_desc=%p dma_eof_desc=%p", eof_desc, eof_desc->owner, eof_desc->len, i2s_out->dma_write_desc, i2s_out->dma_eof_desc);
+
+      for (struct dma_desc *desc = eof_desc; desc >= i2s_out->dma_out_desc; desc--) {
+        i2s_dma_desc_reset(desc);
+      }
+    } else if (i2s_out->dma_eof_desc != eof_desc) {
+      LOG_ISR_WARN("end desc=%p owner=%u len=%u, dma_write_desc=%p dma_eof_desc=%p", eof_desc, eof_desc->owner, eof_desc->len, i2s_out->dma_write_desc, i2s_out->dma_eof_desc);
+
+      for (struct dma_desc *desc = eof_desc; desc > i2s_out->dma_eof_desc; desc--) {
+        i2s_dma_desc_reset(desc);
+      }
+    } else {
+      LOG_ISR_DEBUG("end desc=%p owner=%u len=%u, dma_write_desc=%p dma_eof_desc=%p", eof_desc, eof_desc->owner, eof_desc->len, i2s_out->dma_write_desc, i2s_out->dma_eof_desc);
+    }
+
+    i2s_out->dma_eof_desc = eof_desc;
+
+    // unblock get() task
+    xEventGroupSetBitsFromISR(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_DMA_EOF, task_wokenp);
+
+    // XXX: e.g. flash writes seem to drop I2S_OUT_TOTAL_EOF_INT_ST?
+    if (!(xEventGroupGetBitsFromISR(i2s_out->event_group) & (I2S_OUT_EVENT_GROUP_BIT_DMA_TOTAL_EOF))) {
+      LOG_ISR_WARN("end -> total_eof, dma_write_desc=%p dma_eof_desc=%p", eof_desc, eof_desc->owner, eof_desc->len, i2s_out->dma_write_desc, i2s_out->dma_eof_desc);
+
+      // unblock flush() tasks
+      xEventGroupSetBitsFromISR(i2s_out->event_group, I2S_OUT_EVENT_GROUP_BIT_DMA_TOTAL_EOF, task_wokenp);
+    }
+
+  } else {
+    LOG_ISR_DEBUG("ignore desc=%p owner=%u len=%u", eof_desc, eof_desc->owner, eof_desc->len);
+  }
 
   i2s_intr_clear(i2s_out->dev, I2S_OUT_EOF_INT_CLR);
 }
@@ -68,6 +138,9 @@ void IRAM_ATTR i2s_intr_handler(void *arg)
 
   taskENTER_CRITICAL_ISR(&i2s_out->mux);
 
+  if (int_st & I2S_OUT_TOTAL_EOF_INT_ST) {
+    i2s_intr_out_total_eof_handler(i2s_out, &task_woken);
+  }
   if (int_st & I2S_OUT_DSCR_ERR_INT_ST) {
     i2s_intr_out_dscr_err_handler(i2s_out, &task_woken);
   }
@@ -89,21 +162,22 @@ int i2s_out_intr_setup(struct i2s_out *i2s_out, const struct i2s_out_options *op
 {
   esp_err_t err = 0;
 
-  LOG_DEBUG("intr=%p", i2s_out->intr);
+  if (i2s_out->intr) {
+    return 0;
+  }
 
   taskENTER_CRITICAL(&i2s_out->mux);
 
   i2s_intr_disable_all(i2s_out->dev);
-
-  if (!i2s_out->intr) {
-    err = esp_intr_alloc(i2s_irq[i2s_out->port], I2S_INTR_ALLOC_FLAGS, i2s_intr_handler, i2s_out, &i2s_out->intr);
-  }
+  err = esp_intr_alloc(i2s_irq[i2s_out->port], I2S_INTR_ALLOC_FLAGS, i2s_intr_handler, i2s_out, &i2s_out->intr);
 
   taskEXIT_CRITICAL(&i2s_out->mux);
 
   if (err) {
     LOG_ERROR("esp_intr_alloc: %s", esp_err_to_name(err));
     return -1;
+  } else {
+    LOG_DEBUG("intr=%p", i2s_out->intr);
   }
 
   return 0;