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    19 repositories

    • PeakRDL-halcpp

      Public
      C++ 17 Hardware abstraction layer generator from systemrdl
      embeddedprogrammingcpu
      embeddedprogrammingcpucppprocessorriscvcpp17risc-vsystemrdlsystemrdl-compiler
      C++
      •
      GNU Lesser General Public License v3.0
      •8•15•2•3•Updated Apr 12, 2026Apr 12, 2026

    • SoCMake

      Public
      CMake based hardware build system
      cmakeasicfpga
      cmakeasicfpgavhdlbuild-automationverilogbuild-systemsystemverilogsystemcintegrated-circuits
      CMake
      •
      GNU Lesser General Public License v3.0
      •7•37•21•7•Updated Apr 1, 2026Apr 1, 2026

    • x-heep

      Public
      eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
      C
      •
      Other
      •137•0•0•0•Updated Mar 23, 2026Mar 23, 2026

    • PeakRDL-socgen

      Public
      Python
      •
      GNU General Public License v3.0
      •1•0•3•0•Updated Mar 23, 2026Mar 23, 2026

    • PeakRDL-opentitan

      Public
      SystemRDL <-> Opentitan regtool hjson format exporter, importer
      Python
      •
      GNU General Public License v3.0
      •5•6•1•0•Updated Feb 27, 2026Feb 27, 2026

    • SoCMake_pruned

      Public
      CMake based hardware build system
      CMake
      •
      GNU Lesser General Public License v3.0
      •7•0•0•0•Updated Feb 16, 2026Feb 16, 2026

    • PeakRDL-regblock

      Public
      Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
      Python
      •
      GNU Lesser General Public License v3.0
      •61•0•1•0•Updated Feb 10, 2026Feb 10, 2026

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      •
      Other
      •312•0•0•0•Updated Jan 13, 2026Jan 13, 2026

    • riscv-dbg

      Public
      RISC-V Debug Support for our PULP RISC-V Cores
      SystemVerilog
      •
      Other
      •90•0•0•0•Updated Apr 3, 2025Apr 3, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •194•1•0•0•Updated Apr 3, 2025Apr 3, 2025

    • UVVM_SoCMake

      Public
      UVVM SoCMake support repository
      CMake
      •0•0•0•0•Updated Feb 20, 2025Feb 20, 2025

    • apb_crc_uvm_socmake

      Public
      C++
      •
      GNU General Public License v3.0
      •1•0•0•0•Updated Feb 11, 2025Feb 11, 2025

    • svuvm-socmake

      Public
      SystemVerilog UVM SoCMake package
      CMake
      •1•1•0•0•Updated Feb 9, 2025Feb 9, 2025

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •16•0•0•0•Updated Jan 20, 2025Jan 20, 2025

    • picorv32_socmake

      Public
      PicoRV32 - A Size-Optimized RISC-V CPU
      Verilog
      •
      ISC License
      •931•0•0•0•Updated Dec 4, 2024Dec 4, 2024

    • pulpissimo

      Public
      This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      •
      Other
      •193•0•0•0•Updated Oct 17, 2024Oct 17, 2024

    • verilog-perl

      Public
      Verilog parser, preprocessor, and related tools for the Verilog-Perl package
      Perl
      •
      Artistic License 2.0
      •40•0•0•0•Updated Sep 2, 2024Sep 2, 2024

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •42•0•0•0•Updated Aug 29, 2024Aug 29, 2024

    • riscv-gnu-toolchain

      Public
      GNU toolchain for RISC-V, including GCC
      C
      •
      Other
      •1.4k•0•0•0•Updated May 6, 2024May 6, 2024
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