Releases: m96-chan/NxPU
Releases · m96-chan/NxPU
v0.3.0
What's Changed
- ci: bump actions/upload-pages-artifact from 3 to 4 by @dependabot[bot] in #107
- ci: bump actions/checkout from 4 to 6 by @dependabot[bot] in #108
- ci: bump actions/download-artifact from 4 to 7 by @dependabot[bot] in #109
- ci: bump actions/upload-artifact from 4 to 6 by @dependabot[bot] in #110
- deps: bump prost from 0.13.5 to 0.14.3 by @dependabot[bot] in #112
- deps: bump tract-onnx from 0.21.10 to 0.22.0 by @dependabot[bot] in #113
- Improve test coverage for core crates by @m96-chan in #114
- Add fuzz testing for WGSL parser by @m96-chan in #115
- Implement real vendor NPU backends (#104) by @m96-chan in #116
- feat: embed constant weights into ONNX output (#117) by @m96-chan in #118
New Contributors
- @dependabot[bot] made their first contribution in #107
Full Changelog: v0.2.0...v0.3.0
v0.2.0 — Test Coverage & CI Hardening
NxPU v0.2.0
テストカバレッジ拡充、CI強化、リリース品質改善のアップデートです。
Added
- Numerical correctness tests for tanh, conv2d, maxpool, and attention ops (#101)
- CLI unit tests for argument parsing, precision, and opt-level validation (#99)
- Workspace-level lint configuration with clippy pedantic (#98)
cargo-denylicense audit in CI (#97)- Feature flags for backend selection (
backend-onnx,backend-tflite, etc.) (#95)
Fixed
- Move miette
fancyfeature to CLI-only to reduce dependency footprint (#96) - Fix MSRV CI and doc env for Windows (#102, #103)
- Fix security audit CI job permissions
- Resolve release quality issues #85-#92
Changed
- Annotate dev-only workspace dependencies (#93)
Full Changelog: v0.1.0...v0.2.0
v0.1.0 — Initial Release
NxPU v0.1.0
WGSL → NPU transpiler の初回リリースです。
Added
- WGSL-to-NPU transpiler with arena-based SSA IR
nxpu-parser: WGSL parsing via naga with lowering to NxPU IRnxpu-ir: Intermediate representation with types, expressions, statements, and compute graphsnxpu-opt: Optimization pass framework with fixed-point iteration- Constant folding, FMA fusion, dead code elimination, IR validation
- Quantization passes (F32 → F16, BF16, Int8, mixed-precision)
- Shape inference and memory layout assignment (NHWC/NCHW)
nxpu-analysis: Pattern classification (MatMul, Conv2D, ElementWise, Pool, Activation, Reduce, Transpose, Reshape, Normalization, Concat, Split, Attention) and fusion with tensor name connectivitynxpu-backend-core: Backend trait, plugin registry, IR dump backend- Backend emitters: ONNX, TFLite, CoreML, StableHLO
- Vendor backends: Samsung, MediaTek, Intel, AMD, Qualcomm, Arm Ethos, CEVA, Rockchip
nxpu-cli: CLI with target selection, optimization levels, precision control,--list-targets,RUST_LOGsupport- End-to-end tests covering all backends, error paths, and numerical validation
- Documentation: architecture guide, backend implementer guide, CHANGELOG, CONTRIBUTING, SECURITY
Full Changelog: https://github.com/m96-chan/NxPU/commits/v0.1.0