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initial merge b4 rebase. csr can now write to mtvec, added fence as a nop #67

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initial merge b4 rebase. csr can now write to mtvec, added fence as a nop #67

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2a5cf75
csr implemented, needs testing
May 2, 2019
684d5a3
csr implemented, needs testing, cleaned verilog stuff
May 2, 2019
f470ef2
Delete Top.DualPortedMemory.memory.v
nganjehloo May 2, 2019
efcbabf
Delete firrtl_black_box_resource_files.f
nganjehloo May 2, 2019
466ebd9
resolved test file conflict again
May 15, 2019
a753229
resolved test file conflict 3rd time
May 15, 2019
c37e759
resolved lab merge conflicts
May 15, 2019
8a808d4
corrected csr to regfile wiring, enable mie by default
May 11, 2019
29f3755
added mret in InsTest
May 11, 2019
374a9fc
corrected csrrwi reg enable flag, addes all csrrx tests
May 11, 2019
fb8eb48
added incomplete misaligned mem exception handeling
May 13, 2019
d510b17
csr and system calls finsihed and tested, fully working, commented co…
May 14, 2019
561b99e
unaligned mem access code wasn't push for some reason
May 15, 2019
666880f
1st step cleanup
May 15, 2019
c839878
reverted test binary
May 15, 2019
159b1c6
more cleanup
May 15, 2019
f39aed7
forgot to remove merge tag in lab2test
May 15, 2019
e318c68
removed csr test params from lab2test grader, and fivecycle option
May 15, 2019
951de83
refactored csr to avoid using utils, restored helpers.scala
May 16, 2019
e987292
refactored csr to avoid using utils, restored helpers.scala
May 16, 2019
0cc9d93
refactored csr to avoid using utils, restored helpers.scala, added co…
May 16, 2019
336d7f3
Removed CSR stuff for time being until we find a good way of testing it
May 16, 2019
a6e1b2a
removed csr from grading tests
May 16, 2019
9508e1d
corrected a missing line in CPUTesterDriver
May 16, 2019
1b6a645
fixed some tests failing
May 16, 2019
381b251
added comment to credit rocket chip for some implementation details
May 16, 2019
4ad7ac5
csr unit class created
May 2, 2019
1245fb5
Delete firrtl_black_box_resource_files.f
nganjehloo May 2, 2019
9fe73e6
added mret in InsTest
May 11, 2019
8909899
corrected csrrwi reg enable flag, addes all csrrx tests
May 11, 2019
0f45753
added incomplete misaligned mem exception handeling
May 13, 2019
5d03a23
csr and system calls finsihed and tested, fully working, commented co…
May 14, 2019
28142a5
unaligned mem access code wasn't push for some reason
May 15, 2019
3167ed1
removed csr test params from lab2test grader, and fivecycle option
May 15, 2019
8e8afe4
added comment to credit rocket chip for some implementation details
May 16, 2019
491c563
cleaned generated verilog and verilator
May 2, 2019
8c9df1a
Delete Top.DualPortedMemory.memory.v
nganjehloo May 2, 2019
b749de0
removed useless headers in csr, rebuilt binaries for testing
May 15, 2019
08d41c1
resolved merge csr testing changes with old testing
May 15, 2019
bda6e07
added csr debug to single cycle, added test for csrrc instruction
May 15, 2019
bd6d381
corrected csr to regfile wiring, enable mie by default
May 11, 2019
96582af
moved verilator testbench to different folder, deleted more verilog f…
May 15, 2019
352295a
reverted test binary to use original compiled versions
May 15, 2019
2e5f72d
removed initializing registers through add instruction
May 15, 2019
a3923fc
forgot to remove merge tag in lab2test
May 15, 2019
ebb25aa
refactored csr to avoid using utils, restored helpers.scala
May 16, 2019
2c0af03
removed util header from csr
May 16, 2019
dab43b1
added comments for widecounter class, removed mcsr object using UInt …
May 16, 2019
731cf67
Removed CSR from testing for time being until we find a good way of t…
May 16, 2019
059e4d4
removed csr from grading tests
May 16, 2019
10481e0
corrected a missing line in CPUTesterDriver that initializes registers
May 16, 2019
4cbf05e
fixed some tests failing
May 16, 2019
1c642ef
Merge branch 'system_csr' of https://github.com/jlpteaching/dinocpu i…
May 17, 2019
08f734d
added support to write to mtvec register for better traps
May 22, 2019
e1e9871
added support to write to mtvec register for better traps
May 22, 2019
0073f26
Merge branch 'master' of https://github.com/jlpteaching/dinocpu
Jun 18, 2019
877f676
Added fence instruction, and added support to write mtvec csr register
Jun 18, 2019
bdcf521
added support to write to mtvec register for better traps
May 22, 2019
9e02910
initial merge b4 rebase. csr can now write to mtvec, added fence as a…
Jun 18, 2019
3b9c7b4
Forgot to remove merge symbols
Jun 18, 2019
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4 changes: 3 additions & 1 deletion src/main/scala/components/control.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,9 @@ class Control extends Module {
// jalr
BitPat("b1100111") -> List(true.B, false.B, false.B, 2.U, false.B, false.B, true.B, true.B, 0.U, 3.U),
//csr
BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U)
BitPat("b1110011") -> List(true.B, false.B, false.B, 3.U, false.B, false.B, false.B, false.B, 0.U, 0.U),
//fence
BitPat("b0001111") -> List(true.B, false.B, false.B, 4.U, false.B, false.B, false.B, false.B, 0.U, 0.U)
) // Array
) // ListLookup

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13 changes: 10 additions & 3 deletions src/main/scala/components/csr.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -391,7 +391,7 @@ class CSRRegFile extends Module{

//ECALL
when(insn_call){
io.evec := "h80000004".U
io.evec := reg_mtvec.asUInt()
reg_mcause.interrupt := MCauses.machine_ecall & "h80000000".U
reg_mcause.exceptioncode := MCauses.machine_ecall & "h7fffffff".U
}
Expand Down Expand Up @@ -444,8 +444,15 @@ class CSRRegFile extends Module{
reg_mstatus.sd := 0.U
}

//MTVEC IS FIXED IN THIS IMPLEMENTATION

//MTVEC
/* write address to trap too
*/
when (decoded_addr(MCSRs.mtvec)) {
val new_mtvec = wdata.asTypeOf(new MTVec())
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@powerjg powerjg Jun 18, 2019

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Can't you just say reg_mtvec := wdata.asTypeOf(new MTVec())?

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@nganjehloo nganjehloo Jun 20, 2019

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I suppose I could. I just wanted to be explicit in case of any weird optimization trickery. Should I change it?

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@powerjg powerjg Jun 20, 2019

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It's up to you.

reg_mtvec.base := new_mtvec.base
reg_mtvec.mode := 0.U //support direct addressing onl
}

//MDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION

//MIDELEG DOES NOT EXIST IN M-MODE IMPLEMENTATION
Expand Down