Enable and verify interrupt support for RV32E

[helium729]

Enabled VIGNA_CORE_INTERRUPT and VIGNA_CORE_ZICSR_EXTENSION in vigna_conf_rv32e.vh. Refactored vigna_core.v to use dedicated registers for critical CSRs (mstatus, mie, etc.) to handle concurrent updates correctly and fix simulation issues. Fixed interrupt taking logic to ensure proper PC update. Updated interrupt_test.v to fix MIE verification.

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PR created automatically by Jules for task 9841344695408057129 started by @helium729

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