ts4300 lpm

arch/arm64/boot/dts/freescale/Makefile

@@ -585,6 +585,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-ts4300-16.dtbo
 DTC_FLAGS_imx93-ts4300-16 := -@
 dtb-$(CONFIG_ARCH_MXC) += imx93-ts4300-16-mipi2dp.dtbo
 DTC_FLAGS_imx93-ts4300-16-mipi2dp := -@
+dtb-$(CONFIG_ARCH_MXC) += imx93-ts4300-ld.dtbo
+DTC_FLAGS_imx93-ts4300-ld := -@
 
 dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb.dtb \
 			  imx91-9x9-qsb-can1.dtb \

arch/arm64/boot/dts/freescale/imx93-ts4300-ld.dtso

@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2026 Technologic Systems, Inc. dba embeddedTS
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx93-clock.h>
+
+/ {
+	compatible = "technologic,ts4300";
+};
+
+&lpm {
+	status = "okay";
+	ld-mode-enabled;
+};
+
+&fpga {
+	assigned-clock-rates = <266000000>;
+	clock-frequency = <50000000>;
+};
+
+&usdhc1 {
+	assigned-clocks = <&clk IMX93_CLK_USDHC1>;
+	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
+	assigned-clock-rates = <266000000>;
+};
+
+&usdhc2 {
+	assigned-clocks = <&clk IMX93_CLK_USDHC2>;
+	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
+	assigned-clock-rates = <266000000>;
+};
+
+&usdhc3 {
+	assigned-clocks = <&clk IMX93_CLK_USDHC3>;
+	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
+	assigned-clock-rates = <266000000>;
+};

arch/arm64/boot/dts/freescale/imx93-ts4300.dts

@@ -189,6 +189,10 @@
 	};
 };
 
+&ele_fw2 {
+	memory-region = <&ele_reserved>;
+};
+
 &aips2 {
 	fpga: fpga@425e0000 {
 		#address-cells = <1>;

arch/arm64/boot/dts/freescale/imx93-ts9370.dts

@@ -362,6 +362,10 @@
 	};
 };
 
+&ele_fw2 {
+	memory-region = <&ele_reserved>;
+};
+
 &adc1 {
 	vref-supply = <&reg_vref_1v8>;
 	status = "okay";

drivers/soc/imx/imx93_lpm.c

@@ -188,7 +188,6 @@ static unsigned int num_fsp;
 static unsigned int fsp_table[3];
 static struct regulator *soc_reg;
 static struct regmap *regmap;
-static void *se_data;
 DEFINE_MUTEX(mode_mutex);
 
 struct lpm_ctx {
@@ -240,12 +239,19 @@ static void lpm_update_all_clks(struct critical_clk_path *path,
 static void sys_freq_scaling(enum mode_type new_mode)
 {
 	struct critical_clk_path *path = system_run_mode.paths;
+	void *se_data;
 
 	if (new_mode == system_run_mode.current_mode) {
 		pr_debug("System already in target mode, do nothing\n");
 		return;
 	}
 
+	se_data = imx_get_se_data_info(SOC_ID_OF_IMX93, 0);
+	if (!se_data) {
+		pr_err("Unable to get info from secure enclave\n");
+		return;
+	}
+
 	if (new_mode == OD_MODE) {
 		/* increase the voltage first */
 		imx_se_voltage_change_req(se_data, true);
@@ -618,12 +624,6 @@ static int imx93_lpm_probe(struct platform_device *pdev)
 	if (IS_ERR(soc_reg))
 		return PTR_ERR(soc_reg);
 
-	se_data = imx_get_se_data_info(SOC_ID_OF_IMX93, 0);
-	if (!se_data) {
-		dev_err(&pdev->dev, "get se-fw2 failed\n");
-		return -ENODEV;
-	}
-
 	/*
 	 * initial auto clock gating ssi strap, set to 32768 by default,
 	 * too small value will impact the ddr performance significantly.