- We are working on creating some hardware cores using Chisel HDL
- Additionally we have set up a simple development harness to create professional grade tools at zero cost and built it into one package. We support:
- Generating Verilog with Circt & FIRRTL
- Testing With Treadle and Verilator
- Synthesis with Yosys
- Timing Analysis with OpenSTA
- Formal Verification with Chisel Formal & Z3
- Coverage with scala-scoverage for line coverage and our own custom Toggle Coverage Harness
- See Uart.scala and UartTest.scala for examples of how to use our toggle coverage harness
- Documentation and Publishing with LaTeX & Github Actions
- And Finally Package Management with Nix
- See our document on How to use our tools: Usage