Chip Implementation
The Following figure shows an actual chip implementation (along with a high-level block diagram of the modules inside it) of a control part of a channel of the router with handshaking flow control along with the corresponding control part checkers (checkers for LBDR, Arbiter and control part of FIFO). Pre-layout Synthesis has been performed using AMS 0.18 um CMOS technology library.
2nd chip's block diagram can be found in the figure below:
A more abstract version of the block diagram, including 4 processing elements, 4 Network Interfaces, and 4 routers is shown in the following figure:
For fault injectors, since we want to test the checkers in the second chip, we have located the FI modules in the inputs of checkers (which are fed from internal signals and pseudo- and functional outputs of the main circuit, but not the inputs of the circuit), The structure of the fault injector used and the chain between the router components used for feeding in the fault injection values, compatible with IJTAG interface are shown in the following figures:
The chain of the components connected (used for IJTAG) for customized routers in a 2x2 NoC are shown in the following figures (The chip includes the customized routers):
