FSM Sequence Detector (1101)

This Verilog project implements a Finite State Machine (FSM) to detect the serial input sequence 1101.

Files

• seq_det1.v : FSM module for sequence detection.
• seq_det_tb.v : Testbench to simulate the sequence and check output.
• Clock toggles every 5ns (#5), and the input stream is provided serially.

How It Works

The FSM uses 4 states:

• S0 → S1 on 1
• S1 → S2 on 1
• S2 → S3 on 0
• S3 → S0 on 1 (and sets out = 1)

Overlapping sequences are supported.

Simulation

You can simulate using ModelSim, Vivado, or any Verilog simulator.

Expected Output:

• out goes HIGH after detecting the sequence 1101.