seq_det1.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// 
// Engineer: Ghada
// 
// Create Date: 07/01/2025 01:29:29 AM
// Design Name: Seq Detector
// Module Name: seq_det1
// Project Name: fsm-sequence-detector 
// Revisions:
// Revision 0.01 - File Created
// 
//////////////////////////////////////////////////////////////////////////////////
//1101

module seq_det1(
input in,
input rst,
input clk,
output reg out 
   );
parameter S0=3'd0, S1=3'd1, S2=3'd2, S3=3'd3;   
reg [1:0] cs, ns;

always @ (posedge clk or posedge rst)begin
//current state logic
    if(rst)
       cs<=S0;
    else 
        cs<=ns;
end
//ns & out logic                
always @(*)
begin
     out<=0;
     case(cs)
     S0: if (in)
            ns<=S1;
         else    
            ns<=S0;
     S1: if (in)
             ns<=S2;
         else
             ns<=S1;
     S2:  if (!in)
             ns<=S3;
          else
             ns<=S2;
     S3:  if (in)begin
             ns<=S0;
             out<=1;
             end
          else begin
             ns<=S3;
             out<=0;
             end                                  
    endcase
end                          
endmodule
module seq_det_tb;
    reg rst,in,clk;
    wire out;

 seq_det1 uut (
        .in(in),
        .rst(rst),
        .clk(clk),
        .out(out)
    );
    
    always #5 clk=~clk;
    initial begin
        clk=0 ;rst = 1; in = 0;
        #10;
        rst = 0;

        // Apply serial bits: sequence = 1 1 0 1
        in = 1; #10;
        in = 1; #10;
        in = 0; #10;
        in = 1; #10;// At this point, output should go high
        
        // Another sequence (with overlap)
         in = 1; #10;
         in = 0; #10;
         in = 1; #10;
         in = 1; #10;
         in = 0; #10;
         in = 1; #10;
         
end
        
endmodule