7-Segment-Display-Driver-Simulation

This project simulates a 7-segment display driver using Verilog. The DE1 module converts a 4-bit binary input (W, X, Y, Z) into segment outputs (A-G) using OR and AND gates. The TestBench module tests the design by simulating inputs and verifying 7-segment display outputs, highlighting digital logic and hardware simulation concepts.

Project Files

DE1 Module:

• Converts a 4-bit binary input (W, X, Y, Z) to outputs (A, B, C, D, E, F, G) that control the 7-segment display.
• Utilizes OR and AND gates to derive the segment signals from the input values.
• Inverts inputs to create internal signals for logical operations.

TestBench Module:

• Simulates various input combinations to test the DE1 module.
• Displays the segment outputs for each input combination to verify correctness.
• CircuitVerse File
• The CircuitVerse file is an autogenerated netlist code for a 7-segment display driver. It includes the following components:

Input Inversion:

• Inverts the inputs W, X, Y, and Z to create notW, notX, notY, and notZ.

OR Gates:

• Combines different inputs and their inversions to produce intermediate signals (or_0_out to or_16_out).

AND Gates:

• Uses the intermediate OR gate outputs to create the final segment outputs (and_0_out to and_6_out).

Output Assignments:

• Assigns the AND gate outputs to the corresponding segments (A to G) of the 7-segment display. TestBench:
• Initializes inputs and simulates different input combinations.
• Displays the resulting segment outputs to verify the DE1 module's functionality.

How to Use

Simulation:

• Use a Verilog simulator like Icarus Verilog at https://www.edaplayground.com/ to run the simulation.
• Load the DE1 and TestBench modules into the simulator.
• Observe the segment outputs for various input combinations to ensure the display driver works correctly.

Testing:

• The TestBench module runs through different binary inputs and prints the segment outputs.
• Compare the displayed outputs with the expected results to verify the correctness.