Chapters 7 to 10

AR/07_memory/07_memory.tex

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+% Source: CPTR 280 Computer Organization and Assembly Language Fall 2023
+% File: "07 Memory (key).pdf"
+% Author: James Foster, pogil@jgfoster.net
+
+% comment out for student version
+% \ifdefined\Student\relax\else\def\Teacher{}\fi
+
+\documentclass[12pt]{article}
+
+\title{Activity 7: Memory}
+\author{James Foster}
+\newcommand{\activityeditor}{James Foster}
+\newcommand{\activitysource}{\url{pogil@jgfoster.net}}
+\date{Fall 2023}
+
+\input{../../cspogil.sty}
+\usepackage{graphicx}
+\usepackage{tabularx}
+
+\begin{document}
+
+  \begin{center}
+    \maketitle
+    \rolenames
+  \end{center}
+
+  \keyquestions{
+  \item Model 1, Question \#10
+  \item Model 2, Question \#14
+  \item Model 3, Question \#21
+  }
+
+  \newpage
+  \maketitle
+
+  In previous activities, we explored combinational logic circuits where outputs depend only on current inputs.
+  However, computers need to remember information—they need memory. This activity introduces sequential logic circuits,
+  where outputs depend on both current inputs and previous states. We'll build up from the simplest memory element (a flip-flop that stores one bit)
+  to more complex circuits that can store and retrieve multiple bits using addresses. Understanding how memory works at the hardware level is fundamental to
+  grasping how computers store programs, data, and maintain state during execution.
+
+  \guides{
+    \item Students will be able to explain how a flip-flop maintains state using feedback.
+    \item Students will be able to distinguish between level-triggered and edge-triggered D flip-flops.
+    \item Students will be able to describe how addressable memory uses select lines to read or write specific memory locations.
+    \item Students will be able to trace the flow of data through memory circuits.
+   }{
+    \item Analyzing circuit diagrams to understand data storage and retrieval.
+    \item Comparing different types of flip-flops and their timing characteristics.
+    \item Collaborating to trace signals through sequential circuits and build understanding collectively.
+   }{
+    No additional notes
+   }{
+    \item \url{https://www.codehiddenlanguage.com/}
+   }
+
+  \input{feedback.tex}
+  \newpage
+  \input{flip_flop.tex}
+  \newpage
+  \input{level_trigger_d_flip_flop.tex}
+  \newpage
+  \input{edge_triggered_d_flip_flop.tex}
+  \newpage
+  \input{addressable_memory.tex}
+
+\end{document}

AR/07_memory/addressable_memory.tex

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+\model{Addressable Memory}
+
+  The latch from Model D has two inputs for each bit, a write line and a data line. If you were going to build many such latches
+  (think millions or billions), it would be nice to have a way to let them share the write and data lines and do the selection with fewer lines.
+  For example, a thousand separate locations could be identified with only 10 lines and a billion locations could be identified with 30 lines.
+  Think of each location as having a unique integer address.
+
+  {\it\large Refer to Model 5 above as your team develops consensus answers
+  to the questions below.}
+
+  \quest{10 min}
+
+  \Q Consider the following 3-to-8 decoder. It has eight latches below (not shown), but only a single data in line and write line. A three-bit address is added on the left.
+    \vspace{10pt}
+    \begin{center}
+      \includegraphics[width=0.6\textwidth]{figures/decoder_fig13.png}
+      \par\vspace{5pt}
+      {\small Figure 13}
+    \end{center}
+    \begin{enumerate}
+      \item If the write line is 1 and each of the address lines (A0, A1, and A2) are 0, what are the output values for the 4-input AND gates labeled 7 to 0?
+        \vspace{10pt}
+        \begin{center}
+          \begin{tabular}{|c|c|c|c|c|c|c|c|}
+            \hline
+            7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\
+            \hline
+            \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{1} \\
+            \hline
+          \end{tabular}
+        \end{center}
+
+      \item If the write line is 1 and each of the address lines are 1, what are the values for the 4-input AND gates labeled 7 to 0?
+        \vspace{10pt}
+        \begin{center}
+          \begin{tabular}{|c|c|c|c|c|c|c|c|}
+            \hline
+            7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\
+            \hline
+            \ans[0.2in]{1} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} & \ans[0.2in]{0} \\
+            \hline
+          \end{tabular}
+        \end{center}
+
+      \item Generalize the relationship between the address lines and the AND gates.
+        \begin{answer}[0.75in]
+          The address lines make up a binary number equal to the AND gate number.
+        \end{answer}
+    \end{enumerate}
+
+  \Q Just like it would be nice to have a single data-in line for many latches, it would be nice to have a single data-out line.
+    An 8-input OR gate would have a 1 output if any of the latches had a 1 output. How could you modify Figure 13 to select which latch to read?
+    (After thinking about it, see Figure 14 for a hint!)
+    \begin{answer}[1.5in]
+      Have each 4-input AND gate receive three inputs from the address lines (as before) but have the fourth input for each be the output of the respective flip-flop.
+      So the output of the AND gate would be 1 if the address selected that gate and the flip-flop had a 1 as well.
+    \end{answer}
+
+  \vspace{10pt}
+  \begin{center}
+    \includegraphics[width=0.7\textwidth]{figures/addressable_memory_fig14.png}
+    \par\vspace{5pt}
+    {\small Figure 14}
+  \end{center}
+
+  \vspace{10pt}
+  Figure 14 shows an addressable 8-bit array of memory. The address control lines specify which bit to read or write. There is a single data-in line that can be used to store to memory (if the write control line is enabled) and read from memory.
+  Instead of storing eight bits these circuits could be stacked eight high to store eight bytes. The address and write control lines would be shared, and the data lines would be unique for each bit of the byte (so 20 lines total).
+  Instead of having only eight locations (with a three-bit address), these circuits could be expanded to have (say) a 16-bit address and 65,536 locations (64 KiB of RAM).
+  We now have addressable memory!

AR/07_memory/edge_triggered_d_flip_flop.tex

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+  \model{Edge-Triggered D-Type Flip-Flop}
+
+  \quest{10 min}
+
+  \Q What simple change would be required to have the flip-flop in Model C remember\key\\[-2.5mm] the data value when the write line is 0 (instead of 1)?
+    \begin{answer}[1in]
+      Add an inverter to the input so that it is interpreted as 1 instead of 0.
+    \end{answer}
+
+  \Q The following figure shows two level-trigger D-type flip-flops, along with two inputs (write and data), and one output.
+    Connect the inputs so that the first flip-flop latches the data value when the write line is 0 (the switch is open).
+    Connect the second flip-flop so that it latches the output of the first flip-flop when the write line is 1. Connect the output of the second flip-flop to the LED on the right.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.6\textwidth]{figures/edge_triggered_fig12_solution.png}
+      \else
+        \includegraphics[width=0.6\textwidth]{figures/edge_triggered_fig12.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 12}
+    \end{center}
+
+  This circuit is an edge-triggered D-type flip-flop that latches a value only when the write line has a positive transition from 0 to 1. Note that Figure 12 is slightly different from that shown on page 229 of the text, but the behavior is the same (which do you like better and why?).

AR/07_memory/feedback.tex

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+\model{Feedback}
+
+  Recall that a relay consists of a coil of wire around a ferromagnetic material (such as iron) with a switch that is pulled toward
+  the coil when electricity flows because the coil becomes magnetic. The switch connects an input signal or wire to one of two output
+  terminals depending on whether electricity is flowing.
+
+  \vspace{10pt}
+  \begin{center}
+    \includegraphics[width=0.35\textwidth]{figures/oscillating_relay.png}
+    \par\vspace{5pt}
+    {\small Figure 1: Oscillating Relay}
+  \end{center}
+
+  {\it\large Refer to Model 1 above as your team develops consensus answers
+  to the questions below.}
+
+  \quest{10 min}
+
+  \Q When the switch is open, does electricity flow through the circuit?
+    \hfill\ans[1in]{no}
+
+  \Q When the switch is initially closed, does electricity start to flow through the circuit?
+    \begin{answer}[0.5in]
+      yes
+    \end{answer}
+
+  \Q What happens to the coil on the relay soon after step 2?
+    \hfill\ans{It becomes magnetized}
+
+  \Q What happens to the bar on the relay soon after step 3?
+    \hfill\ans{It switches (drops down) to the other pole}
+
+  \Q What happens to the circuit after step 4?
+    \hfill\ans{Electricity stops flowing}
+
+  \Q What happens to the coil soon after step 5?
+    \hfill\ans{It becomes demagnetized}
+
+  \Q What happens to the bar soon after step 6?
+    \hfill\ans{It switches (up) to the top pole}
+
+  \Q What happens to the circuit after step 7?
+    \hfill\ans{Electricity starts flowing again}
+
+  \Q Summarize what happens when the switch is closed (steps 2-8).
+    \begin{answer}[0.75in]
+      The relay switches back and forth continuously.
+    \end{answer}
+
+  \Q Recall that an inverter switches a 0 to 1 and a 1 to 0. What is the output of the\key\\[-2.5mm] following circuit?
+    \vspace{10pt}
+    \begin{center}
+      \includegraphics[width=0.3\textwidth]{figures/inverter_feedback.png}
+      \par\vspace{5pt}
+      {\small Figure 2: Inverter Feedback}
+    \end{center}
+
+    \begin{answer}[0.75in]
+      It continuously switches between on and off.
+    \end{answer}
+
+  \vspace{10pt}
+  Feedback occurs when the output of a circuit is ``fed back'' into the input of the circuit. You have heard what happens when the sound from a PA system's speaker gets into a microphone!

AR/07_memory/flip_flop.tex

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+\model{Flip-Flop}
+
+  Recall that the output from a NOR gate is 1 only when both inputs are 0.
+  If either input is 1 then the output is 0.\\
+
+  {\it\large Refer to Model 2 above as your team develops consensus answers
+  to the questions below.}
+
+  \quest{10 min}
+
+  \Q Complete Figure 3 by showing both switches open and highlight (in red if you can) any portion of the circuit with high voltage (assuming both inputs to the left NOR are both 0).
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig3_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig3.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 3}
+    \end{center}
+
+  \Q With the circuit in the state shown in Figure 3, imagine that Switch 1 is closed. Complete Figure 4 highlighting any portion of the circuit with high voltage.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig4_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig4.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 4}
+    \end{center}
+
+  \Q With the circuit in the state shown in Figure 4, imagine that Switch 1 is opened. Complete Figure 5 highlighting any portion of the circuit with high voltage.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig5_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig5.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 5}
+    \end{center}
+
+  \Q Both Figures 3 and 5 have both switches open. How are they different?\key\\[-2.5mm]
+    \begin{answer}[0.75in]
+      The light is off in Figure 3 and on in Figure 5.
+    \end{answer}
+
+  \Q With the circuit in the state shown in Figure 5 (Switch 1 is open), imagine that Switch 2 is closed. Complete Figure 6 highlighting any portion of the circuit with high voltage.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig6_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig6.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 6}
+    \end{center}
+
+  \Q With the circuit in the state shown in Figure 6, imagine that Switch 2 is opened. Complete Figure 7 highlighting any portion of the circuit with high voltage.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig7_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/flipflop_fig7.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 7}
+    \end{center}

AR/07_memory/level_trigger_d_flip_flop.tex

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+\model{Level-Trigger D-Type Flip-Flop}
+
+  \quest{10 min}
+
+  \Q Recall that an AND gate has an output of 1 only if both inputs are 1. In Figure 8 enter the value 0 for Write, Data, and output (Q). Highlight the lines that have high voltage for this state to exist.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.5\textwidth]{figures/level_trigger_fig8_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/level_trigger_fig8.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 8}
+    \end{center}
+
+  \Q With the circuit in the state shown in Figure 8, imagine that Data changes from 0 to 1. Highlight the lines in Figure 9 that have high voltage and update Q.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.5\textwidth]{figures/level_trigger_fig9_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/level_trigger_fig9.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 9}
+    \end{center}
+
+  \Q With the circuit in the state shown in Figure 9, imagine that Write changes from 0 to 1. Highlight the lines in Figure 10 that have high voltage and update Q.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.4\textwidth]{figures/level_trigger_fig10_solution.png}
+      \else
+        \includegraphics[width=0.4\textwidth]{figures/level_trigger_fig10.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 10}
+    \end{center}
+
+  \Q With the circuit in the state shown in Figure 10, imagine that Write changes from 1 to 0. Highlight the lines in Figure 11 that have high voltage and update Q.
+    \vspace{10pt}
+    \begin{center}
+      \ifdefined\Teacher
+        \includegraphics[width=0.6\textwidth]{figures/level_trigger_fig11_solution.png}
+      \else
+        \includegraphics[width=0.5\textwidth]{figures/level_trigger_fig11.png}
+      \fi
+      \par\vspace{5pt}
+      {\small Figure 11}
+    \end{center}
+
+  We now have a circuit that latches onto (remembers) a data line only when the write line is 1.