We built a 2-way out-of-order super-scalar RISC-V core based on Intel P6 microarchitecture.
The baseline is the version we submit for EECS 470.
- Average CPI: 1.88
- Period: 15ns
Below picture is the performance we achieved at the end of this course.
wshenyi/EECS-470-FinalProject
Folders and files
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