InstructionFormat

From rtl/control.v, it appears that iDEA supports several instruction format paterns.

• Type R instructions are regular two register input, one register output instructions. This class includes normal arithmetic and logical functions.
• Type I instructions support one register input, one register output, and a sixteen-bit immediate value. This class includes arithmetic and logical operations with immediates and conditional branches based on comparison of the register to the immediate.
• Type J instructions include an absolute branch instruction with twenty one-bit immediate for absolute address. (What is the JAL instruction?)

Table of instruction formats:

 31     25    20    15    10    5   0
|opcode|  ra |  rb |  rd | ??  |funct|    Type R
|opcode|  ra |  rd |  immediate      |    Type I
|opcode|   target?                   |    Type J

Questions:

• It looks like instruction JAL is hard-coded to do something with register 31. Is this correct? What does it do? Is this something like a "return from subroutine" instruction, and register 31 is the return address? (Just guessing.)

• What happened to the three register read instructions like madd and mac and msub?

• It looks like instead of the simple LDR and STR instructions have been replaced by the traditional long list of instructions for loading/storing different widths. True?

The new ISA reuses a subset of MIPS-I instructions with minor changes:

Instruction             Operation                                                     Comment
ADD[U]   rd, rs, rt     rd[31..0] <-    rs[31..0]  +   rt[31..0]                      both ADD and ADDU opcodes does the same for iDEA 
ADDLB    rd, rs, rt     rd[31..0] <-    rs[31..0]  +   rt[31..0]                      w/ internal loopback, specific to iDEA
SUB[U]   rd, rs, rt     rd[31..0] <-    rs[31..0]  -   rt[31..0]                      both SUB and SUBU opcodes does the same for iDEA 
SUBLB    rd, rs, rt     rd[31..0] <-    rs[31..0]  -   rt[31..0]                      w/ internal loopback, specific to iDEA
AND      rd, rs, rt     rd[31..0] <-    rs[31..0]  &   rt[31..0]
ANDLB    rd, rs, rt     rd[31..0] <-    rs[31..0]  &   rt[31..0]                      w/ internal loopback, specific to iDEA
OR       rd, rs, rt     rd[31..0] <-    rs[31..0]  |   rt[31..0]
ORLB     rd, rs, rt     rd[31..0] <-    rs[31..0]  |   rt[31..0]                      w/ internal loopback, specific to iDEA
XOR      rd, rs, rt     rd[31..0] <-    rs[31..0]  ^   rt[31..0]
XORLB    rd, rs, rt     rd[31..0] <-    rs[31..0]  ^   rt[31..0]                      w/ internal loopback, specific to iDEA
NOR      rd, rs, rt     rd[31..0] <-    rs[31..0]  ^  ~rt[31..0]
NORLB    rd, rs, rt     rd[31..0] <-    rs[31..0]  ^  ~rt[31..0]                      w/ internal loopback, specific to iDEA
JR       rs             pc        <-    rs[31..0]                 
MULT     ???            ???
MULTU    ???            ???
SLL      rd, a?, b?     rd[31..0] <-    a?[31..0]  <<  b?[4..0]
SLLV     rd, a?, b?     rd[31..0] <-    a?[31..0]  <<  b?[4..0]
SRL      rd, a?, b?     rd[31..0] <-    a?[31..0]  >>  b?[4..0] 
SRLV     rd, a?, b?     rd[31..0] <-    a?[31..0]  >>  b?[4..0]
SRA      rd, a?, b?     rd[31..0] <-   (a?[31..0]  >>  b?[4..0]) | {a?[31],0[30..0]}
SRAV     rd, a?, b?     rd[31..0] <-   (a?[31..0]  >>  b?[4..0]) | {a?[31],0[30..0]}
SLT      rd, rs, rt     rd[31..0] <-    rs[31..0]  < rt[31..0] ? 1 : 0
SLTU     rd, rs, rt     rd[31..0] <- {0,rs[31..0]} < {0,rt[31..0]} ? 1 : 0
ADDI[U]  rt, rs, imm16  rt[31..0] <-    rs[31..0]  +   sx32(imm16[15..0])             both ADDI and ADDIU opcodes does the same for iDEA 
ADDILB   rt, rs, imm16  rt[31..0] <-    rs[31..0]  +   sx32(imm16[15..0])             w/ internal loopback, specific to iDEA
ANDI     rt, rs, imm16  rt[31..0] <-    rs[31..0]  &   sx32(imm16[15..0])
ANDILB   rt, rs, imm16  rt[31..0] <-    rs[31..0]  &   sx32(imm16[15..0])             w/ internal loopback, specific to iDEA
OR       rt, rs, imm16  rt[31..0] <-    rs[31..0]  |   sx32(imm16[15..0])
ORLB     rt, rs, imm16  rt[31..0] <-    rs[31..0]  |   sx32(imm16[15..0])             w/ internal loopback, specific to iDEA
XOR      rt, rs, imm16  rt[31..0] <-    rs[31..0]  ^   sx32(imm16[15..0])
XORLB    rt, rs, imm16  rt[31..0] <-    rs[31..0]  ^   sx32(imm16[15..0])             w/ internal loopback, specific to iDEA
J        imm??          pc        <-    sx32(imm??)                 
JAL      imm??          pc, r31   <-    sx32(imm??), pc
SLTI     rt, rs, imm16  rt[31..0] <-    rs[31..0]  < sx32(imm16) ? 1 : 0
SLTIU    rt, rs, imm16  rt[31..0] <- {0,rs[31..0]} < {0,sx32(imm16)} ? 1 : 0
LUI      rt, imm16      rt[31..0] <- imm16 << 16
BEQ      rs, rt         ???
BNE      rs, rt         ???
BGTZ     rs             ???
BGEZ     rs             ???
BLTZ     rs             ???
BLEZ     rs             ???
LBU      rt, rs(imm16)  ???
LH       rt, rs(imm16)  ???
LW       rt, rs(imm16)  ???
SB       rt, rs(imm16)  ???
SH       rt, rs(imm16)  ???
SW       rt, rs(imm16)  ???

Note:

• JALR (indirect call to a function) is missing in iDEA.

• LB would have been more sensitive than LBU since LBU can be done with a pair (LB,ANDI) while a sign extension of LBU is more complex to do so (no SEXT/ZEXT in iDEA).