GitHub - vachanukb04/16-Bit_CPU_Design: Designed, Simulated and Synthesized a 16-Bit CPU in Verilog HDL. The design involved RTL coding for counter, ALU, CPU controller, Instruction register and data memory. · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 20 Commits
ALU_topfile.v		ALU_topfile.v
Barrel_shifter.v		Barrel_shifter.v
CPU_16bit.pdf		CPU_16bit.pdf
CPU_topfile.v		CPU_topfile.v
Capture.PNG		Capture.PNG
Capture1.PNG		Capture1.PNG
Data_mem.v		Data_mem.v
Instruction_reg.v		Instruction_reg.v
Logic_Unit.v		Logic_Unit.v
README.md		README.md
processor_top.v		processor_top.v
program_counter.v		program_counter.v
q1(1).PNG		q1(1).PNG
reg_ab.v		reg_ab.v
reg_c.v		reg_c.v
tb_cpu.v		tb_cpu.v

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16-Bit CPU Design in Verilog HDL

Components used:

ALU-Arithmetic Unit, Logical Unit, Shifter
Data Memory
Program Counter
Instruction memory
Instruction Register
Multiplexers
Controller

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Designed, Simulated and Synthesized a 16-Bit CPU in Verilog HDL. The design involved RTL coding for counter, ALU, CPU controller, Instruction register and data memory.

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Verilog 100.0%