Skip to content

fix: pulls reg declaration up #7

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
filmil wants to merge 1 commit into
base: master
Choose a base branch
from
Open

fix: pulls reg declaration up #7

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 5 additions & 2 deletions src_v/ddr3_axi_pmem.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -170,6 +170,9 @@ reg prio_rd_q;

// Round robin priority between read and write
wire write_prio_w = ~prio_rd_q || !axi_arvalid_i;

reg awvalid_q;
wire awvalid_w = axi_awvalid_i | awvalid_q;
wire read_prio_w = prio_rd_q || !awvalid_w;

always @ (posedge clk_i )
Expand All @@ -188,7 +191,7 @@ wire read_enable_w = read_prio_w & ~read_limit_w;
//-------------------------------------------------------------
// Write Buffer
//-------------------------------------------------------------
reg awvalid_q;
//reg awvalid_q;
reg [31:0] awaddr_q;
reg [7:0] awlen_q;
reg [3:0] awid_q;
Expand Down Expand Up @@ -228,7 +231,7 @@ begin
awid_q <= axi_awid_i;
end

wire awvalid_w = axi_awvalid_i | awvalid_q;
//wire awvalid_w = axi_awvalid_i | awvalid_q;
wire [31:0] awaddr_w = awvalid_q ? awaddr_q : axi_awaddr_i;
wire [7:0] awlen_w = awvalid_q ? awlen_q : axi_awlen_i;
wire [3:0] awid_w = awvalid_q ? awid_q : axi_awid_i;
Expand Down