Project to implement a simple LC2K processor in SystemVerilog. Planned for FPGA deployment.
Verilog tasks:
- Implementing single cycle datapath
- Implementing pipeline datapath
- Hazard forwarding In Progress
- Implementing PC
- Implementing ALU
- Implementing Register File
- Implementing Memory
- Implementing Control FSM
- Implementing a cache
- Implementing a branch predictor
- Testing
Based primarily on descriptions from Dan Liu's course notes. I did the datapath work for the JALR command.