India RISC-V Reference SoC Tapeout Program Phase 2 personal documentation
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Updated
Dec 31, 2025 - Verilog
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scl180nm
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This repository contains documentation and relevant materials for the RISC-V SoC Tapeout Program, a collaborative initiative between IIT Gandhinagar, VLSI System Design (VSD), and other prominent organizations in the field of semiconductor design.
simulation verification rtl verilog gls synopsys risc-v caravel pdk chip-design functional-simulation scl180nm
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Updated
Jan 5, 2026 - Verilog
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