ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
The road to tapeout is real. Welcome to my assignment hub! Physical Design w/ASICs Aug-Dec'23
This Repo is to demonstrate RTL to GDSII design implementation
A synthesizable SPI Master–Slave full-duplex communication module implemented in Verilog HDL. This repository covers the complete RTL-to-GDS flow using Cadence tools, including RTL design, verification, synthesis, place-and-route, and timing analysis.
This repository contains the report of the Week 2 task for VSD RV SoC Tapeout Program
End-to-end Microwatt-based SoC with AXI-Lite, Wishbone, and APB buses, fully verified using Cocotb and taken from RTL to GDSII on Sky130 using OpenLane.
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