Verilog module to transmit/receive to/from RGMII compatible ethernet PHY

A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.

iCE40 and ECP5 fpga libraries and projects. Using the open source toolchain yosys+nextpnr. Quality may vary.

UDP/IP parser for RGMII - Initial implementation (wrong interface for Arty A7). Lesson: Read hardware docs first! See MII versions for correct implementation.