FPGA-based 4-digit stopwatch implemented in Verilog HDL on Basys 2 FPGA. Demonstrates synchronous counters, FSM control, 7-segment multiplexing, and hardware resource optimization. Highlights skills in digital design and embedded systems.
fsm fpga stopwatch embedded-systems verilog multiplexing 7-segment-display hardware-optimization xilinx-basys2 synchronous-counters mini-project-simulation
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Updated
Jan 5, 2026 - Verilog