Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)
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Updated
Jan 17, 2025 - Verilog
Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)
This repository contains the hardware layout and verification IP for the implementation of Okapi in the RISC-V core BOOM.
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