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@rp15 rp15 commented Jan 10, 2026

Enabled RISC-V hex code generation along with the already existing CGRA SV verification for the FIR vector global reduce VectorCGRA SV test.

@rp15 rp15 requested a review from tancheng January 10, 2026 07:04
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tancheng commented Jan 10, 2026

I thought the test was already enabled in previous PR. So this PR does some cleanup or bug fix (then why it passed before)?

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rp15 commented Jan 14, 2026

I thought the test was already enabled in previous PR. So this PR does some cleanup or bug fix (then why it passed before)?

Good question; this PR is adding capability to generate RISC-V hex code to be used with the coredac accelerator SOC test bench. Not changing any of the functionality of this CGRA-only tb.

@rp15 rp15 merged commit 002f62d into tancheng:master Jan 14, 2026
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2 participants