Support Handling each PLIC interrupt on each hart on multi-core

[aidenschoi]

Hi,
I have an issue.

The implementation of freedom-metal should be considered about PLIC interrupt handling on multi-core. But, currently, PLIC can be handled on only 1 core that registers an interrupt at first among several cores. For example, when the PLIC interrupt of BTN0 is registered on hart0 and PLIC of BTN1 is registered on hart1, only BTN0 works on hart0 and BTN1 doesn't work. Because mtvec and mie of only one core are enabled normally and other cores keep initial value - early_trap_vector (mtvec) and NULL (mie) instead of the address of __metal_exception_handler() (mtvec) and 0x800 (MEIE in mie).

So. I modified 2 files for this problem.
The modification in riscv_cpu.c is to enable mtvec on each core.
The modification in riscv_plic0.c is to set mie to 0x800 (MEIE) on each core.

Please refer IPOBHD-176 for detail.

Thanks,
Aiden.

[keith-packard]

The issue underlying this bug is that Freedom Metal does not correctly support CPU interrupt configuration in multi-HART systems. Configuration of the CPU interrupt controller can only be done by instructions executing on the target CPU. Freedom Metal has no way to get a particular core to execute those instructions. This patch does not solve that problem. It may make some code work in some environments which does not work today, but that's essentially entirely accidental.