Releases: sharc-lab/LightningSim
Releases · sharc-lab/LightningSim
v0.2.5
v0.2.4
- Fixed missing implementations for
hls::stream<float>andhls::stream<double> - Fixed bad kernel invocation for designs that use
array_partitionon top-level ports, which was previously causing segfaults
v0.2.3
- Fixed runtime implementation of arbitrarily sized FIFO channels, which was previously causing segfaults in certain designs
- If you continue to face problems, please file an issue.
- Fixed linker issues related to the frequently-used
@llvm.part.selectand@llvm.part.setintrinsics
v0.2.2
- Fixed linker issues across Vitis HLS versions
- Added CLI mode, which is now the default
- CLI mode is non-interactive and does not support manipulating FIFO depths in the simulation. For this behavior, please use the existing GUI mode, which can now be launched by providing the
--guiflag. - A message is displayed to ease migration. This message will be removed in a future version; for now, it can be suppressed by explicitly passing the
--cliflag.
- CLI mode is non-interactive and does not support manipulating FIFO depths in the simulation. For this behavior, please use the existing GUI mode, which can now be launched by providing the
- Added build for Python 3.11
- We now provide pre-built packages for Python 3.10–3.12. If you would like us to distribute packages for another Python version, please file an issue.
v0.2.1
- Updated packaging for LightningSimV2, which now supplants the original
lightningsimconda package - Fixed several linker issues to try to be more generic across environments and Vitis HLS versions
- Improved minor quality-of-life features (e.g., smarter automatic port selection for web server)
LightningSimV2
This is LightningSimV2, a faster and scalable simulation tool for high-level synthesis via graph compilation and optimization.
v0.1.0
- Optimized stall calculation, especially when a design makes many calls to submodules, by avoiding traversing the module hierarchy
- Optimized trace generation by replacing templated
fprintfcalls withfputscalls with precomputed strings - Added progress meter (including estimated time remaining) for trace resolution and stall calculation steps
- Added code to the benchmarking script to generate
details.txtfor each benchmark, which reports the start and end cycles for each module in the module hierarchy - Improved error reporting for failed subprocesses during trace generation by including stdout/stderr in the error message
- Fixed incorrect expected counts of FIFO reads/writes in some edge cases, which caused trace parsing to fail for some designs
- Fixed usage of relative paths during testbench compilation, which sometimes caused trace generation to fail when using relative paths to the solution directory
This release includes breaking API changes in the lightningsim.simulator module. Specifically, the Simulator.active_subcalls property has been renamed to subcalls to better reflect its actual purpose, and the Simulator.events property has been removed, having been replaced by the Simulator.subcall_inits and Simulator.stalls properties.
v0.0.3
- Fixed handling of reserved function names (
read,write) in Vitis HLS - Fixed missing runtime dependency on
libedit - Fixed unnecessary
#include <gmp.h>in FlowGNN benchmarks, which breaks those benchmarks on some systems
v0.0.2
v0.0.1
- Initial public release of LightningSim