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Machine Opcodes
General-purpose registers (GPR) are a to h.
Most of the commands take GPRs as operands, few take constants or no arguments at all.
Mnemonics:
- Rx - GPR-type operand number 'x' (starting from 1)
- M[x] - memory at address 'x'
- Ux - unsigned constant number 'x'
- Sx - signed constant number 'x'
- L[n] - peripheral on line 'n'
Hidden registers:
- IP - instruction pointer register
- SP - stack pointer register
- II - interrupts inhibited
Hidden registers cannot be used directly.
Everything is 32-bit.
Files that follow the syntax below are translated by the SASM assembler into a loadable binary.
Syntax: hlt
Operation: Stops Emulation
The Opcode is 0x00, which makes it easier to detect bugs
Syntax: nop
Operation: none
After execution, the emulation thread sleeps for 0.1 seconds
Syntax: jmp R1
Operation: IP -> R1
Syntax: ldc U1 R2
Operation: U1 -> R2
Syntax: mrm R1 R2
Operation: R1 -> M[R2]
Syntax: mmr R1 R2
Operation: M[R1] -> R2
Syntax: out R1
Operation: signal -> L[R1]
Sends signal to peripheral in a given line
Syntax: jgt R1 R2
Operation: if R1 .gt 0 jmp R2
Syntax: opn
Operation: 0 -> II
When interrupts are enabled, a signal from a peripheral leads to a call of the corresponding interrupt handler.
Syntax: cls
Operation: 0 -> II
Syntax: ldr S1 R2
Operation: IP + S1 -> R2
Reads from memory from address calculated from instruction pointer and given signed constant.
Syntax: lsp R1
Operation: R1 -> SP
Syntax: push R1
Operation: R1 -> [SP++]
The stack grows from a lower address to a higher one.
Syntax: pop R1
Operation: [SP--] -> R1
Syntax: int
Operation: INT L[0]
Causes virtual loopback device (located on line 0) to trigger an interrupt signal.
Syntax: cll R1
Operation: push IP + 4; jmp R1
Support functions and procedures: saves return address on the stack and then jumps to given address.
Syntax: ret
Operation: JMP [SP--]
Fetch the return address from the stack and jump there.
Syntax: irx
Operation: equivalent of pop h-a; ret; opn
Performs a procedure that is a reverse of peripheral interrupt: restores all registers from the stack, returns the address fetches from the stack, and re-enables interrupts.
When the stack pointer is changed by the interrupt handler, this constitutes a context switch.
Syntax: ssp R1
Operation: SP -> R1
Syntax: mrr R1 R2
Operation: R1 -> R2
The set of arithmetic and bitwise operations performed on 32-bit words.
Syntax: inv R1 R2
Operation: ~R1 -> R2
Syntax: add R1 R2 R3
Operation: R1 + R2 -> R3
Syntax: sub R1 R2 R3
Operation: R1 - R2 -> R3
Syntax: mul R1 R2 R3
Operation: R1 * R2 -> R3
Syntax: div R1 R2 R3
Operation: R1 // R2 -> R3
Syntax: mod R1 R2 R3
Operation: R1 % R2 -> R3
Syntax: rsh R1 R2 R3
Operation: R1 >> R2 -> R3
Syntax: lsh R1 R2 R3
Operation: R1 << R2 -> R3
Syntax: bor R1 R2 R3
Operation: R1 | R2 -> R3
Syntax: xor R1 R2 R3
Operation: R1 ^ R2 -> R3
Syntax: band R1 R2 R3
Operation: R1 & R2 -> R3
Syntax: spm R1 R2
Operation: PM enabled; R1 -> MMU low address; R2 -> MMU high address
Syntax: lpm R1
Operation: Violation status -> R1
Syntax: cpt U1
Operation: none
Before execution, the emulator prints out checkpoint number (U1) to stdout and registers contents to stderr.
Syntax: aeq R1 C2
Operation: none
Upon execution, the emulator compares R1 and C2. If not equal, emulation stops with a non-null error code.