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3 changes: 3 additions & 0 deletions rhdl-core/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,9 @@ syn = "2.0.38"
tempfile = "3.8.1"
vcd = "0.7.0"

[dev-dependencies]
rhdl = { path = "../rhdl" }

[features]
default = ["svg", "iverilog"]
svg = ["dep:svg"]
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5 changes: 2 additions & 3 deletions rhdl-core/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -44,12 +44,11 @@ pub use codegen::verilog::generate_verilog;
pub use codegen::verilog::VerilogModule;
pub use compiler::compile_design;
pub use note_db::note;
pub use note_db::note_init_db;
pub use note_db::note_reset_db;
pub use note_db::note_pop_path;
pub use note_db::note_push_path;
pub use note_db::note_take;
pub use note_db::note_take_vcd;
pub use note_db::note_time;
pub use note_db::NoteDB;
pub use schematic::components::BlackBoxComponent;
pub use schematic::components::BlackBoxTrait;
pub use schematic::constraints::constraint_input_synchronous;
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