GitHub - sabhp143/uvm-testbench-tutorial-simple-adder: A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
driver_direct_testbench		driver_direct_testbench
Makefile.vcs		Makefile.vcs
README		README
simpleadder.v		simpleadder.v
simpleadder_agent.sv		simpleadder_agent.sv
simpleadder_config.sv		simpleadder_config.sv
simpleadder_driver.sv		simpleadder_driver.sv
simpleadder_env.sv		simpleadder_env.sv
simpleadder_if.sv		simpleadder_if.sv
simpleadder_monitor.sv		simpleadder_monitor.sv
simpleadder_pkg.sv		simpleadder_pkg.sv
simpleadder_scoreboard.sv		simpleadder_scoreboard.sv
simpleadder_sequencer.sv		simpleadder_sequencer.sv
simpleadder_tb_top.sv		simpleadder_tb_top.sv
simpleadder_test.sv		simpleadder_test.sv

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How to run
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This Makefile is made to be used with Synopsys VCS but it should be easily adaptable to any SystemVerilog simulator.

To run the simulation you just need to type:

	$ make -f Makefile.vcs


Configuration
-------------

You'll need to edit the Makefile.vcs file and change the variable 'UVM_HOME' to your UVM installation.


Explanation of the code
-----------------------

An explanation of this UVM testbench can be found at: http://colorlesscube.com/uvm-guide-for-beginners/