Welcome to my comprehensive Digital Design learning journey! This repository documents my exploration of digital systems, hardware description languages, and low-level programming concepts.
This project demonstrates a simple 2-input AND gate written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/and_gate.v - Testbench:
verilog/basics/and_gate_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for an AND gate:
| a | b | y (a & b) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
This project demonstrates a simple 2-input OR gate written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/or_gate.v - Testbench:
verilog/basics/or_gate_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for an OR gate:
| a | b | y (a | b) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
This project demonstrates a simple NOT gate (inverter) written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/not_gate.v - Testbench:
verilog/basics/not_gate_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for a NOT gate:
| a | y (~a) |
|---|---|
| 0 | 1 |
| 1 | 0 |
This project demonstrates a simple 2-input XOR gate written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/xor_gate.v - Testbench:
verilog/basics/xor_gate_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for a XOR gate:
| a | b | y (a ^ b) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
This project demonstrates a simple 2-input XNOR gate written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/xnor_gate.v - Testbench:
verilog/basics/xnor_gate_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for a XNOR gate:
| a | b | y (a ~^ b) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
This project demonstrates a simple 2-input NOR gate written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/nor_gate.v - Testbench:
verilog/basics/nor_gate_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for a NOR gate:
| a | b | y ~(a | b) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
This project demonstrates a simple 2-input NAND gate written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/nand_gate.v - Testbench:
verilog/basics/nand_gate_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for a NAND gate:
| a | b | y ~(a & b) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
This project demonstrates a simple buffer gate written in Verilog, along with its testbench and waveform output.
- Source:
verilog/basics/buffer.v - Testbench:
verilog/basics/buffer_tb.v - Waveform Screenshot:
The waveform shows the expected truth table for a buffer gate:
| a | y |
|---|---|
| 0 | 0 |
| 1 | 1 |
This repository serves as a knowledge base and practical workspace for:
- Digital Design Fundamentals - Logic gates, combinational & sequential circuits
- C Programming - Low-level programming, embedded systems, and hardware interfacing
- Verilog HDL - Hardware description and digital system modeling
DigitalDesign/
├── 📁 digital-design/ # Digital design theory and projects
│ ├── 📁 combinational/ # Combinational logic circuits
│ ├── 📁 sequential/ # Sequential logic & state machines
│ ├── 📁 memory/ # Memory systems and storage
│ └── 📁 processors/ # CPU design and architecture
├── 📁 c-programming/ # C language learning and projects
│ ├── 📁 basics/ # Fundamentals and syntax
│ ├── 📁 embedded/ # Embedded C programming
│ ├── 📁 hardware-interface/ # Hardware communication
│ └── 📁 projects/ # Practical implementations
├── 📁 verilog/ # Verilog HDL code and designs
│ ├── 📁 basics/ # Basic Verilog concepts and gates
│ ├── 📁 modules/ # Reusable Verilog modules
│ ├── 📁 testbenches/ # Simulation and testing
│ └── 📁 fpga-projects/ # FPGA implementation projects
├── 📁 images/ # Simulation screenshots and diagrams
└── 📄 README.md # Main documentation
- Boolean algebra and logic minimization
- Combinational circuit design (multiplexers, decoders, encoders)
- Sequential circuit design (flip-flops, counters, registers)
- State machine design and implementation
- Memory systems (RAM, ROM, cache)
- Computer architecture fundamentals
- Timing analysis and clock domains
- C fundamentals and syntax
- Pointers and memory management
- Bit manipulation and bitwise operations
- Embedded C programming
- Hardware register manipulation
- Interrupt handling
- Real-time programming concepts
- Verilog syntax and modeling styles
- Behavioral vs. structural modeling
- Combinational and sequential logic in Verilog
- Testbench development
- Synthesis considerations
- FPGA implementation
- Timing constraints and analysis
- Text Editor/IDE: VS Code with Verilog extensions
- C Compiler: GCC/MinGW for Windows
- Verilog Simulator: ModelSim, Vivado, or open-source alternatives
- FPGA Tools: Xilinx Vivado, Intel Quartus, or Lattice Diamond
- Version Control: Git
- Development boards (Arduino, FPGA boards)
- Logic analyzers and oscilloscopes
- Breadboards and basic electronic components
- "Digital Design and Computer Architecture" by Harris & Harris
- "The C Programming Language" by Kernighan & Ritchie
- "Verilog HDL: A Guide to Digital Design and Synthesis" by Palnitkar
- Nandland - FPGA and Verilog tutorials
- HDLBits - Verilog practice problems
- Ben Eater's YouTube Channel - Digital logic explanations
- IEEE 1364 Verilog Standard
- C11 Standard (ISO/IEC 9899:2011)
- FPGA vendor documentation
Learning Phase: Create files anywhere in the repository as you learn and experiment. Don't worry about perfect organization initially - focus on understanding concepts and building things!
Organization Phase: Later, we'll sort and move files into the structured folders shown above based on what you've learned and created.
# Compile and run a C program (Windows PowerShell)
gcc -o program.exe program.c
.\program.exe# Basic Verilog compilation (using Icarus Verilog)
iverilog -o simulation.vvp module.v testbench.v
vvp simulation.vvp- Clone or download this repository
- Install required tools (GCC/MinGW, Verilog simulator)
- Configure your development environment
- Start creating files and learning - organization comes later!
📋 Current Approach: Files are created in the root directory during active learning 🗂️ Future Organization: Files will be moved to appropriate folders in the structure above 📂 Temp Files: Keep experimenting! We'll sort everything later
- Aug 17, 2025 - Added NOR, XNOR, XOR, NOT, OR, AND gate Verilog projects and updated documentation
- Aug 7, 2025 - Initial repository setup and README creation
- Learning area currently being studied
- Specific project or concept being implemented
- Next milestone or goal
This section will track files that need to be moved to proper folders:
- List of files created during learning sessions
- Notes on which folder each file should go to
- Any files that need renaming or restructuring
This is a personal learning repository, but if you find errors or have suggestions:
- Feel free to open an issue
- Suggest improvements or additional resources
- Share alternative implementations or approaches
This repository is for educational purposes. Code examples and implementations are provided as-is for learning and reference.
- Thanks to the digital design community for excellent resources
- Appreciation for open-source tools that make learning accessible
- Recognition of educators and content creators in this field
Happy Learning! 🚀
Last Updated: August 2025
"The best way to learn digital design is to build something." - Keep experimenting and building!