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Contradictory xithreshold description

Status: Open.

#763 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 5, 2026

Interrupt priority and threshold fields cannot have the same width

Status: Open.

#762 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 4, 2026

Smip/Ssip limited by fixed 6-register scope

Status: Open.

#758 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 3, 2026

Unclear interrupt identity storage

Status: Open.

#756 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 3, 2026

Tail chaining breaks preemption level handling

Status: Open.

#755 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 3, 2026

Incomplete late preemption description

Status: Open.

#754 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 3, 2026

Incorrect motivation for stack pointer swapping

Status: Open.

#753 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 3, 2026

Conditional instructions violate RISC-V style

Status: Open.

#752 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 3, 2026

Ambiguous "second fetch" recommendation

Status: Open.

#751 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 2, 2026

Conflicting trap handler address formula

Status: Open.

#750 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 2, 2026

Undefined "required side-effects"

Status: Open.

#749 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 2, 2026

Useless VTMASK in vector table mode

Status: Open.

#748 In riscv/riscv-fast-interrupt;

· reosdev opened on Feb 2, 2026