Add serial link version with delay lines

Bender.yml

@@ -26,6 +26,10 @@ sources:
     - src/regs/serial_link_reg_top.sv
     - src/regs/serial_link_single_channel_reg_pkg.sv
     - src/regs/serial_link_single_channel_reg_top.sv
+    - src/regs/serial_link_delay_line_reg_pkg.sv
+    - src/regs/serial_link_delay_line_reg_top.sv
+    - src/regs/serial_link_single_channel_delay_line_reg_pkg.sv
+    - src/regs/serial_link_single_channel_delay_line_reg_top.sv
 
     # Parametrization
     - src/serial_link_pkg.sv
@@ -39,25 +43,34 @@ sources:
     - src/serial_link_network.sv
     - src/serial_link_data_link.sv
     - src/serial_link_physical.sv
+    - src/serial_link_physical_delay_line.sv
 
-    # Serial Link Wrapper
+    # Serial Link top level
     - src/serial_link.sv
 
+    # Serial Link wrapper for single-channel/multi-channel selection
+    - src/serial_link_wrapper.sv
+
     # Wrapper for Occamy
     - src/serial_link_occamy_wrapper.sv
 
     - target: synthesis
       files:
       - src/serial_link_synth_wrapper.sv
 
-    - target: any(simulation, test)
+    - target: slink_test
       files:
       - test/axi_channel_compare.sv
-
-    - target: test
-      files:
       - test/tb_axi_serial_link.sv
       - test/tb_ch_calib_serial_link.sv
       - test/tb_stream_chopper.sv
       - test/tb_stream_chopper_dechopper.sv
       - test/tb_channel_allocator.sv
+
+    - target: any(test, simulation)
+      files:
+      - models/configurable_delay.behav.sv
+
+    - target: fpga
+      files:
+      - models/configurable_delay.fpga.sv

Makefile

@@ -42,14 +42,16 @@ update-regs: src/regs/*.hjson
 	echo $(REGGEN)
 	$(REGGEN) src/regs/serial_link.hjson -r -t src/regs
 	$(REGGEN) src/regs/serial_link_single_channel.hjson -r -t src/regs
+	$(REGGEN) src/regs/serial_link_delay_line.hjson -r -t src/regs
+	$(REGGEN) src/regs/serial_link_single_channel_delay_line.hjson -r -t src/regs
 
 # --------------
 # QuestaSim
 # --------------
 
 TB_DUT ?= tb_axi_serial_link
 
-BENDER_FLAGS := -t test -t simulation
+BENDER_FLAGS := -t slink_test -t simulation
 
 VLOG_FLAGS += -suppress vlog-2583
 VLOG_FLAGS += -suppress vlog-13314

models/configurable_delay.behav.sv

@@ -0,0 +1,39 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Thomas Benz <tbenz@iis.ee.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+//
+// Based on work of:
+// Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
+// Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+
+
+// Automatically generated by the Generic Delay generator.
+`timescale 1ps/1ps
+
+(* no_ungroup *)
+(* no_boundary_optimization *)
+module configurable_delay #(
+  parameter int unsigned NUM_STEPS, // The desired number of delay taps. Must be
+  // a power of 2. Don't use very large values
+  // here, otherwise strategy to just let STA
+  // (with the right SDC) do the job for us
+  // will not work.
+  localparam DELAY_SEL_WIDTH = $clog2(NUM_STEPS)
+) (
+  input  logic       clk_i,
+  input  logic       enable_i,
+  input  logic [DELAY_SEL_WIDTH-1:0] delay_i,
+  output logic clk_o
+);
+
+  logic enable_latched;
+  logic clk;
+
+  assign clk = clk_i;
+
+  always @(clk) clk_o <= #(real'(delay_i)*3.750ns/15) clk;
+
+endmodule

models/configurable_delay.fpga.sv

@@ -0,0 +1,38 @@
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Thomas Benz <tbenz@iis.ee.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+//
+// Based on work of:
+// Fabian Schuiki <fschuiki@iis.ee.ethz.ch>
+// Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+
+`timescale 1ps/1ps
+
+(* no_ungroup *)
+(* no_boundary_optimization *)
+module configurable_delay #(
+  parameter int unsigned NUM_STEPS, // The desired number of delay taps. Must be
+                                   // a power of 2. Don't use very large values
+                                   // here, otherwise strategy to just let STA
+                                   // (with the right SDC) do the job for us
+                                   // will not work.
+  localparam DELAY_SEL_WIDTH = $clog2(NUM_STEPS)
+) (
+  input logic                       clk_i,
+  input logic                       enable_i,
+  input logic [DELAY_SEL_WIDTH-1:0] delay_i,
+  output logic                      clk_o
+);
+
+  IBUF #
+    (
+     .IBUF_LOW_PWR ("FALSE")
+     ) u_ibufg_sys_clk_o
+      (
+       .I  (clk_i),
+       .O  (clk_o)
+       );
+
+endmodule