SystemRDL integration

[FrancescoConti]

This pull request introduces significant updates to the NEUREKA project, focusing on integrating a SystemRDL-generated register interface, updating the hardware control logic, and modernizing the simulation flow. The most important changes are grouped below by theme.

SystemRDL Register Interface Integration:

• Added SystemRDL-generated NEUREKA register interface files (neureka_regif_pkg.sv, neureka_regif.sv) to the project sources and included a generation script (gen_regif.sh). This enables a more maintainable and structured register interface for the NEUREKA controller. [1] [2]
• Refactored neureka_ctrl.sv to use the new SystemRDL register interface, replacing the legacy HWPE controller slave port and register file logic with the new hwpe_ctrl_target and neureka_regif modules. All register accesses and job control signals now use the new interface. [1] [2] [3]

Dependency and Build System Updates:

• Updated the hwpe-ctrl dependency in Bender.yml to a newer commit that supports the SystemRDL-based flow.
• Adjusted the Makefile and build system to support the new simulation flow with qopt/qsim (replacing vopt/vsim), added handling for the new design.bin file, and updated simulation run commands accordingly. [1] [2] [3] [4]

Testbench and Simulation Improvements:

• Modified tb_dummy_memory.sv to use standard always blocks instead of always_ff for improved compatibility and simulation behavior. [1] [2] [3] [4]