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Fix FPGA synthesizability #34

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Fix FPGA synthesizability #34

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@LuigiGhionda LuigiGhionda commented Jun 2, 2025

This PR fixes FPGA synthesizability by:

  • Forcing the use of FF-based input buffer when targeting FPGA, through a define.
  • Moving wildcard imports inside module header; this is necessary as in some Vivado flows it could result in packages being visible by other files, ending up with conflicting names.

@LuigiGhionda LuigiGhionda changed the title Fix synthesizability Fix FPGA synthesizability Jun 2, 2025
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LuigiGhionda commented Jun 2, 2025 •
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CI seems to be broken @FrancescoConti :(

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@FrancescoConti FrancescoConti Awaiting requested review from FrancescoConti

@arpansur arpansur Awaiting requested review from arpansur

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@LuigiGhionda @alex96295